S32E2 Safe and Secure High-Performance Real-Time Processors with Actuation Support

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  • This page contains information on a preproduction product. Specifications and information herein are subject to change without notice. For additional information contact support or your sales representative.

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S32E2 Real-Time Processors Block Diagram

S32E2 Safe and Secure High-Performance Real-Time Processors with Actuation Support

S32Z and S32E Real-Time Processors Software Block Diagram

S32Z and S32E Real-Time Processors Software Block Diagram

Features

Processors

  • Eight Arm® Cortex®-R52 cores running at up to 1 GHz with flexible split/lock configurations:
    • Two clusters with a pair of dual-core lockstep cores in each cluster
    • One cluster with a pair of dual-core lockstep cores and one cluster with four cores
    • Two clusters of four cores
  • Each Arm Cortex-R52 core includes Arm Neon SIMD technology
  • Lockstep Arm® Cortex®-M33 System Manager core
  • DSP/ML processor (25 GFLOPS)

Memory

  • 19 MB SRAM
  • Up to 64 MB of integrated flash memory
  • 2x QSPI for NOR flash (x1, x4, x8) and HyperRAM memory
  • SD Card/SDIO and eMMC NAND flash support
  • Memory expansion with LPDDR4 interface for DRAM and flash memory (3.2 GB/s)
  • Supports on-the-fly, over-the-air update capability with zero processor downtime

Communications

  • CAN accelerator: flexible, low-latency communications engine (FlexLLCE) with 24 CAN 2.0 / CAN FD interfaces

Networking

  • Integrated time-sensitive networking (TSN) Gigabit Ethernet switch (NETC3)
  • 2x Ethernet MACs each supporting 10/100 Mbps MII/RMII and 100/1000 Mbps RGMII

Timers

  • Complex timer unit (CTU)
  • 2x enhanced modular I/O subsystem (eMIOS)
  • Optional complex timers (GTM 4.1)

Safety

  • Advanced safety functionality and fault recovery
  • Processors are developed according to processes that are certified to ISO/SAE 21434 for cybersecurity and ISO 26262 for ASIL D functional safety

Security

  • Integrated hardware security engine (HSE) for root of trust (RoT)
    • Secure boot, security services and key management
  • Public key infrastructure and side-channel attack resistance
  • Dedicated crypto accelerators for CAN, QSPI and LPDDR4 interfaces
  • Processors are developed according to processes that are certified to ISO/SAE 21434 for cybersecurity and ISO 26262 for ASIL D functional safety

Other

  • AEC-Q100 Grade 1 device with support up to -40 to 150º C (junction)

Documentation

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1 documents

Design Resources

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Hardware

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Software

1 software file

Note: For better experience, software downloads are recommended on desktop.

Training

3 trainings

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