In general, I3C incorporates and unifies key attributes of I2C and SPI while improving the capabilities and performance of each approach with a comprehensive, scalable interface and architecture. The specification also anticipates sensor interface architectures that mobile, mobile-influenced, and embedded-systems industries will need in the future.
The technical features of the MIPI I3C℠ specification define a two-pin interface that is backward compatible with the I2C standard and provide data throughput capabilities comparable to SPI. The technical attributes explain the name for the specification, MIPI Specification for I3C℠, which signifies its compatibility with I2C and the desire of the Working Group to provide a bridge for the industry from past legacy to future innovations.
The new technology can facilitate in-band interrupts within the 2-wire interface, which drastically reduces device pin count and signal paths to enable incorporation of more sensors in a device. On standard CMOS I/O, it supports a minimum data rate of 10 Mbps with options for higher performance high-data-rate (HDR) modes, offering a substantial leap in performance and power efficiency compared to existing options. It also offers multicontroller support, dynamic addressing, command-code compatibility and a uniform approach for advanced power management features, such as sleep mode.
Partner Silvaco takes care of the distribution of MIPI I3C IP Blocks of NXP. Silvaco is a leading EDA provider of Software tools, used in analog/mixed-signal, power IC and memory design.
Headquartered in Santa Clara, California, Silvaco has a global presence with offices located in North America, Europe, Japan, and Asia for over 30 years and is offering fast-turnaround and affordable services for TCAD, SPICE Modeling, and PDK development as well as semiconductor design IP Blocks.
I3C IP is owned by NXP, but packaged, sold, and supported through Silvaco.
The typical sensor classes as addressed by Mipi I3C are:
Mechanical/motion
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Biometric/Health
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Environmental Sensing
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Other
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The area depends on configuration and options and add up to between 1.5K – 2.5K gates for the Target module. The power estimate is technology independent, so an exact number is not possible– however it is a low-power design, very small and thus consumes very little power. It supports clock-gating and other approaches to limit power consumption. The backend can operate without a system clock at all. It consists of two clock domains: the SCL (I3C side) and System (SoC side, when full wrapper is used with APB).
Four different packages are made available
| Product | Description |
| I3C Dual-Role Controller | packaged, under normal IP license from Silvaco |
| Advanced Target | packaged, under normal IP license from Silvaco |
| Autonomous Target | packaged, under normal IP license from Silvaco |
| Configurable RTL (layers and parameters) |
| User Guide (including programming guide) |
| Integration Guide |
| Integration Test Bench with test cases (incl. controller model, protocol monitor, etc.) |