Access Secure Information About Our Products
Sign in to access authorized secure information. Learn more about secure access rights.
The MCX portfolio is a comprehensive selection of Arm® Cortex®-M based MCUs, offering expanded scalability with breakthrough product capabilities, simplified system design and a developer-focused experience through the widely adopted MCUXpresso suite of software and tools. The new simplified system design offers optimal enablement and intelligent peripherals for the intelligent edge including machine learning, wireless, voice, motor control, analog and more. The MCX portfolio is part of NXP’s EdgeVerse™ edge computing platform.
The MCX portfolio features four new series of devices supported by NXP’s widely adopted MCUXpresso suite of software and development tools to simplify product development.
The Arm® Cortex®-M-based MCX portfolio is purpose-built on a common foundation of core technologies that support vast industrial and IoT use cases.
Building on the strength of more than 20 years of industry-leading Kinetis and LPC portfolios, the MCX portfolio debuts a new generation of scalable, secure and developer-focused microcontrollers. The Arm® Cortex®-M based MCX portfolio is purpose-built on a common foundation of core technologies that support vast industrial and IoT use cases. These 32-bit, flash-based microcontrollers provide expanded product capabilities with memory scalability and a broad package offering. A simplified system design offers optimal enablement and intelligent peripherals for the intelligent edge including: machine learning, wireless, voice, motor control, analog and more. The portfolio also features the first instantiation of NXP’s new, specialized neural processing unit (NPU) for accelerating inference at the edge, delivering up to 30x faster machine learning throughput compared to a CPU core alone.
The new MCX MCU portfolio features four new series of devices supported by NXP’s widely adopted MCUXpresso suite of software and development tools to simplify product development.
Machine learning and run-time inference will be supported by NXP’s eIQ® ML software development environment. Developers can utilize the easy-to-use tools offered by eIQ to train ML models targeting either the NPU or the CPU core and deploy them on the MCU. MCX families that are built following NXP’s security-by-design approach will offer a secure boot with an immutable root-of-trust, hardware-accelerated cryptography and, on select families, a built-in EdgeLock® secure subsystem.
The MCX portfolio is not a replacement for Kinetis and LPC portfolios. MCX is a new NXP portfolio that was purpose-built based on our rich history and knowledge of microcontrollers. Our Kinetis and LPC portfolios have been experiencing record demand and are still relevant devices in our industry.
Just like Kinetis and LPC, MCX MCUs will be supported by the widely-downloaded MCUXpresso software and tools. Existing Kinetis and LPC users will find the MCX software development kit (SDK) within MCUXpresso to be very similar, with the difference being at the hardware abstraction layer (HAL); the rest of the drivers are identical.
NXP has one of the broadest offerings of Arm®-based products. The MCX portfolio extends the existing Kinetis and LPC MCU offerings. When higher performance is needed and/or off-chip flash is desired, i.MX RT Crossover MCUs are the recommended devices. Beyond the crossover portfolio, i.MX applications processors offer even higher performance and support open operating systems like Linux OS.
The NXP NPU is a specialized computation core that implements control and arithmetic logic necessary to execute machine learning algorithms.
The NXP NPU is designed to deliver up to 30x faster machine learning throughput compared to a CPU core alone. It is an internal NXP development that provides flexibility to tune the NPU to better meet our customer needs and provides the ability to offer better ongoing support for changing applications and operator support needs when deployed.
The software support is unified over multiple generations and device portfolios with the eIQ® ML SW development environment, creating consistent enablement and support solutions for our customers.
The EdgeLock secure subsystem (ELS) in select MCX families comprises the immutable core security functionality. It is part of the silicon root of trust and features side-channel protected cryptographic acceleration engines, key management and device attestation.
Pre-configured security and key management policies enable device makers to simplify the path to certification and avoid costly mistakes and save development time.
The N series features a highly efficient multicore architecture, an integrated EdgeLock® secure subsystem and a dedicated, on-chip neural processing unit (NPU) for real-time inference.
Share and collaborate with technology enthusiasts to speed up your design, discuss issues and ask or answer questions.
Scalable, high performance, general-purpose Arm® Cortex®-M based MCUs.
Sign in to access authorized secure information. Learn more about secure access rights.
Important: After email verification refresh this page.
Highly secure information about this product is available, request access rights. Learn more about secure access rights.
Note: Your application will be reviewed individually by NXP. A non-disclosure agreement will help expedite this process.
Your request to gain secure access rights has been declined. If you think this has been declined in error, request access again.
Access More. Additional secure (restricted) information is available for this product series. Request additional access.
We are currently processing your secure access rights request. Once processed, a notification will be sent to ${emailId}.
Some files related to your secure access rights are temporary unavailable due to a system error. Please check back.
Your access to some secure information has been disabled while we process the updates you made to your NXP Account > Profile. We'll send you an email when the verification process is completed.
There is no information to display.
500 characters remaining.
*Describe the justification for your access request for the approver.