Advanced Security
Our secure-by-design approach offers secure boot with an immutable root-of-trust, hardware accelerated cryptography and a built-in EdgeLock® Secure Enclave, Core Profile.
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MCX N Series Microcontrollers
MCX N series of highly integrated Arm Cortex-M33 microcontrollers are designed for high performance and low power consumption. MCX N includes intelligent peripherals and on-chip accelerators providing multitasking capabilities and performance efficiency. Select MCX N families include NXP's eIQ® Neutron neural processing unit (NPU) for machine learning applications. The low-power cache enhances system performance, while the dual-bank flash and full ECC RAM support system safety and offer an extra layer of protection and advanced security. These secure MCUs include our EdgeLock® Secure Enclave, Core Profile offering a secure-by-design approach, secure boot with an immutable root-of-trust and hardware-accelerated cryptography.
Speed up development time for general-purpose Arm® Cortex®-M-based products like the MCX N series with MCUXpresso Developer Experience.
Key Features
Core Performance
Powered by dual-core Arm Cortex-M33s, coprocessors, accelerators and intelligent peripherals, the MCX N provides autonomous operation to reduce power consumption and latency.
MCUXpresso Developer Experience
MCUXpresso IDEs, SDK, secure provisioning and configuration tools help speed up development time with high-quality software and tools.
MCX N Series: Push the Edge of What's Possible
Highly integrated, low-power MCUs to provide the ultimate balance of performance and power consumption. It highlights multitasking performance, on-chip accelerators and advanced security.
MCX N Series Products
| Family | Core | Flash | SRAM | Ethernet | DAC | Op Amp | Flexcomm | CAN-FD | Packages |
|---|---|---|---|---|---|---|---|---|---|
| N94 | 2x M33 @150MHz |
2 MB | 512 kB (416 kB w ECC) | 1 | 2x 12b + 1x 14b | 3 | 10 | 2 | VFBGA184, 9x9mm; HLQFP100, 14x14mm; HDQFP172, 16x16mm |
| N54 | 2x M33 @150Mhz |
2 MB | 512 kB (416 kB w ECC) | 1 | 1x 12b | - | 10 | 1 | VFBGA184, 9x9mm; HLQFP100, 14x14mm; HDQFP172, 16x16mm |
| N53 | 2x M33 @150Mhz |
2 MB | 512 kB (416 kB w ECC) | - | 1x 12b | 3 | 10 | 2 | VFBGA184, 9x9mm; HLQFP100, 14x14mm; HDQFP172, 16x16mm |
| N52 | 2x M33 @150Mhz |
2 MB | 512 kB (416 kB w ECC) | - | 2x 12b + 1x 14b | 3 | 10 | - | VFBGA184, 9x9mm; HLQFP100, 14x14mm |
| N24 | 1x M33 @150Mhz |
2 MB | 512 kB (416 kB w ECC) | 1 | 2x 12b + 1x 14b | 3 | 10 | 2 | VFBGA184, 9x9mm; HLQFP100, 14x14mm; HDQFP172, 16x16mm |
| N23 | 1x M33 @150Mhz |
1 MB | 352 kB (416 kB w ECC) | - | - | - | 8 | 2 | VFBGA184, 9x9mm; HLQFP100, 14x14mm; HDQFP172, 16x16mm |
EdgeLock Assurance Program
When you see EdgeLock Assurance, you'll know it's designed to meet industry standards.
Commitment to Longevity
MCX N series are ready to support your development today, tomorrow and beyond through our longevity program. The Product Longevity program ensures a stable supply of products for your embedded designs.
White paper: Bringing more intelligence to the industrial edge
The MCX N94x MCU integrates a dual-core architecture, on-chip accelerators, connectivity, security features and a wealth of analog and digital peripherals for sensing, control and HMI.
Design Resources
Documents
MCX N Factsheet
The MCX N Series of Industrial and IoT (IIoT) MCUs feature our eIQ® Neutron Neural Processing Unit (NPU) for machine learning (ML) acceleration.
Read the factsheetMCX N Highlights
Discover the advanced features and capabilities of the MCX N Series.
Read the overviewMCX N Series Microcontrollers FAQs
Learn more about NXP's MCX N series portfolio of products.
How do I split hard real time control from ML inference, so loops stay deterministic while vision/audio models run efficiently?
Use MCX N94x/N54x with dual Arm Cortex M33 at 150 MHz to run RTOS and control on one core and schedule ML on the other. Offload pre and post processing to PowerQuad DSP and move models to the chip eIQ Neutron NPU so the CPUs sleep longer. SmartDMA handles camera and mic bursts to cut ISR load. If you do not need on device ML, MCX N23x with a single Arm Cortex M33 at 150 MHz and SmartDMA provides a cost optimized control path with the same software flow.
I need a single chip edge hub that moves data between camera/audio, I3C sensors, CAN FD, USB High Speed, Ethernet and SD logging, without CPU starvation. What’s the cleanest topology?
MCX N94x/N54x combine USB HS with HS PHY, 10/100 Ethernet, uSDHC, dual FlexCAN FD, multiple I3C/SAI and FlexIO for parallel or camera plus two DMA engines to stream frames and logs while keeping jitter low. FlexSPI XIP with cache sustains throughput. Where Ethernet or uSD aren’t required, MCX N23x offers USB HS, dual CAN FD, I3C, SAI and SmartDMA for a lower-cost hub.
How do I implement measured boot, attestation and secure OTA (ideally with external XIP flash) without adding a discrete security element?
MCX N94x/N54x and MCX N23x integrate EdgeLock Secure Enclave Core Profile with immutable ROM boot, DICE/PUF identity, dual secure boot modes, authenticated debug and EdgeLock 2GO hooks. External code and data via FlexSPI support on-the-fly encryption and authentication for XIP and OTA rollback using Flash Swap/RWW.
We may start with no on device ML and later add inference, or pivot from connectivity centric to mixed signal/motor control. Can we scale features without respinning the PCB?
MCX N54x for USB HS, SD and smart card and MCX N94x for richer analog and motor control with multi ADC, op amps and eFlexPWM share common packages, such as VFBGA184, HLQFP100 and HDQFP172, enabling pin-stable boards while activating NPU, analog or motor subsystems by SKU.
What gets me to rapid, first pass bring up for multicore + ML (pin mux, clocks, secure boot, RTOS and model deployment)?
For N94x/N54x, the FRDM MCXN947 board brings Ethernet PHY, USB C HS, CAN FD, and camera/SmartDMA headers; for N23x, use FRDM MCXN236. Both integrate with MCUXpresso IDE/SDK, Zephyr, and security provisioning flows, with ready examples for USB, Ethernet, CAN FD, I3C, motor/analog, and NPU bring up (N94x/N54x).