Product Details

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Block Diagram

MPC561 Block Diagram

MPC561 Block Diagram

Features

  • Precise exception model
  • Floating point
  • Extensive system development support
  • On-chip watchpoints and breakpoints
  • Background debug mode (BDM)
  • IEEE®ISTO 5001-1999 NEXUS class 3 debug interface
  • True 5-volt I/O
  • Two time processing units (TPU3) with 8 KB DPTRAM
  • 22-channel MIOS timer (MIOS14)
  • Two queued analog-to-digital converter modules (QADC64_A, QADC64_B) providing a total of 32 analog channels
  • Three TouCAN modules (TOUCAN_A, TOUCAN_B, TOUCAN_C)
  • One queued serial module with one queued SPI and two SCIs (QSMCM) 32 KB static RAM (CALRAM)

Documentation

Quick reference to our documentation types.

1-5 of 94 documents

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Design Resources

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Design Files

5 design files

  • Models

    IBIS models for the MPC561

  • Printed Circuit Boards and Schematics

    MPC564 Evaluation Board Schematics for the MPC561/562/563/564/533/534

  • Printed Circuit Boards and Schematics

    MPC561/MPC563 Evaluation Board Schematics (Orcad)

  • Printed Circuit Boards and Schematics

    MPC561/MPC563 Evaluation Board Schematics (pdf)

  • Printed Circuit Boards and Schematics

    MPC561 OrCad Layout File

Hardware

2 hardware offerings

Software

1 software file

Note: For better experience, software downloads are recommended on desktop.

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