QorIQ® P1021/12 Single- and Dual-Core Multi-Protocol Communications Processors

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  • This page contains information on a product that is not recommended for new designs.

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Block Diagram

Freescale QorIQ P1021/12 Communication Processor Block Diagram

Freescale QorIQ P1021/12 Communication Processor Block Diagram

Features

Core Complex

  • Dual (P1021) or single (P1012) high-performance Power Architecture® e500 cores, 32 KB L1 cache, up to 800 MHz
  • 256 KB L2 cache with ECC, also configurable as SRAM and stashing memory

Networking Elements

  • Three 10/100/1000 Mbps enhanced triple-speed Ethernet controllers (eTSEC)
  • Two SGMII interfaces
  • Support for IEEE® 1588
  • QUICC Engine® module supporting:
    • UTOPIA-L2
    • Four T1/E1/HDLC
    • TDM
    • Two 10/100 Ethernet

Accelerators and Memory Control

  • DDR2/3 32-bit memory controller with ECC support
  • Integrated security engine
    • Protocol support includes SNOW, ARC4, 3DES, AES, RSA/ECC, RNG, single-pass SSL/TLS, Kasumi
    • XOR acceleration

Basic Peripherals and Interconnect

  • Four-lane SERDES up to 3.125 GHz multiplexed across controllers
  • Two PCI Express® Gen1.0 interface controllers
  • Two USB 2.0 controllers
  • Enhanced Local Bus Controller (eLBC)
  • eSDHC
  • Dual I²C, DUART, PIC, DMA, GPIO

Additional Features

Part numbers include: P1012NSE2DFB, P1012NSE2FFB, P1012NSE2HFB, P1012NSN2DFB, P1012NSN2HFB, P1012NXE2HFB, P1012NXN2DFB, P1012NXN2HFB, P1021NSE2DFB, P1021NSE2HFB, P1021NSN2DFB, P1021NSN2HFB, P1021NXE2DFB, P1021NXE2FFB, P1021NXE2HFB, P1021NXN2DFB, P1021NXN2FFB, P1021NXN2HFB, P1021RDB-PC.

Documentation

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Design Resources

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Software

4 software files

Note: For better experience, software downloads are recommended on desktop.

Training

1 trainings

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