QorIQ® P2020 and P2010 Dual- and Single-Core Communications Processors

P2020 End of Life
  • This page contains information on a product that is not recommended for new designs.

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The QorIQ® P2020 and P2010 communications processors deliver high performance per watt for dual- and single-core applications. Using advanced 45nm process technology these CPUs reach frequencies up to 1.33GHz.

Pin-compatible with the QorIQ P1 family devices, the P2020 and P2010 devices offer four interchangeable cost-effective solutions, scaling from a single core at 533 MHz (P1011) to a dual core at 1.33 GHz (P2020) and delivering an impressive 4.5x aggregate frequency range within the same pinout.

Block Diagram

Freescale QorIQ P2020/10 Communication Processor Block Diagram

Freescale QorIQ P2020/10 Communication Processor Block Diagram
Get diagram PDF

Features

Core Complex

  • Dual (P2020) or single (P2010) high-performance Power Architecture® e500 cores
  • Up to 1.33 GHz
  • 32 KB L1 and 512KB L2 caches

Networking Elements

  • Three 10/100/1000 Mbps enhanced three-speed Ethernet controllers (eTSECs)
  • Four SerDes up to 3.125 GHz multiplexed across controllers supporting:
    • Two PCI Express® interfaces
    • Two Serial RapidIO® interfaces
    • Two SGMII interfaces

Accelerators and Memory Control

  • Integrated security engine
  • Protocol support includes SNOW, ARC4, 3DES, AES, RSA/ECC, RNG, single-pass SSL/TLS, Kasumi, XOR acceleration

Basic Peripherals and Interconnect

  • Dual high-speed USB controllers (USB 2.0)
  • eLBC, eSDHC, Dual I²C, DUART, PIC, DMA, GPIO

Additional Features

  • Package: 689-pin temperature-enhanced plastic BGA (TEPBGA2)
  • 0C to 125C Tj -40C to 125C Tj option

Comparison Table

P2010 P2020
Cores 1 2
Core Frequency 800 - 1200 MHz 800 - 1200 MHz
L2 Cache 512KB 512KB
DDR 32/64-bit DDR2/DDR3 32/64-bit DDR2/DDR3
GbE 3 x 10/100/1000 3 x 10/100/1000
PCIe Gen 1.0 3 controllers w/ 4 SERDES 3 controllers w/ 4 SERDES
sRIO 1.2 2 x1 or 1 x4 2 x1 or 1 x4
USB 2.0 1 1
Memory Card SD/MMC SD/MMC
Other interfaces SPI, 2xI²C, DUART SPI, 2xI²C, DUART
Accelerators SEC3.1 SEC3.1

Buy/Parametrics

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N true 0 PSPP2020en 52 Application Note Application Note t789 30 Application Note Software Application Note Software t783 1 Brochure Brochure t518 1 Data Sheet Data Sheet t520 2 Fact Sheet Fact Sheet t523 5 Product Brief Product Brief t532 1 Reference Manual Reference Manual t877 5 Supporting Information Supporting Information t531 2 Technical Notes Technical Notes t521 1 User Guide User Guide t792 1 White Paper White Paper t530 3 en_US 2 1 5 English The QorIQ<sup>&#174;</sup> P2 platform series, which includes the P2020 and P2010 communications processors, delivers unprecedented performance per watt for a wide variety of applications in the networking, telecom, military and industrial markets. The series delivers dual- and single-core frequencies up to 1.2 GHz on a 45nm technology low-power platform. 1228778885836687636815 PSP 229.5 KB None None documents None 1228778885836687636815 /docs/en/fact-sheet/QP20XXFS.pdf 229476 /docs/en/fact-sheet/QP20XXFS.pdf QP20XXFS N N 2016-10-31 Fact Sheet /docs/en/fact-sheet/QP20XXFS.pdf /docs/en/fact-sheet/QP20XXFS.pdf Fact Sheet N Y 736675474163315314 2022-12-07 pdf N en Feb 14, 2020 Fact Sheet t523 Fact Sheet Fact Sheet Y N Fact Sheet 2 2 English This reference manual defines the functionality of the P2020. The chip combines dual Power ArchitectureR e500v2 processor cores with system logic required for networking, wireless infrastructure, and telecommunications applications.&#13;&#10; 1249275244228708113744 PSP 24.2 MB Registration without Disclaimer None documents Extended 1249275244228708113744 /secured/assets/documents/en/reference-manual/P2020RM.pdf 24199412 /secured/assets/documents/en/reference-manual/P2020RM.pdf P2020RM Y N 2016-10-31 P2020 QorIQ Integrated Processor Reference Manual /webapp/Download?colCode=P2020RM /secured/assets/documents/en/reference-manual/P2020RM.pdf Reference Manual N Y 500633505221135046 2022-12-07 pdf Y en Dec 18, 2012 Reference Manual t877 Reference Manual Reference Manual N P2020 QorIQ Integrated Processor Reference Manual false en_US en Data Sheet Data Sheet 2 3 3 English This document describes the electrical characteristics of the P2010. 1302304654412717382496 PSP 2.1 MB Registration without Disclaimer None documents Extended 1302304654412717382496 /secured/assets/documents/en/data-sheet/P2010EC.pdf 2074938 /secured/assets/documents/en/data-sheet/P2010EC.pdf P2010EC documents Y N 2016-10-31 P2010 QorIQ Integrated Processor Hardware Specifications - Data Sheets /webapp/Download?colCode=P2010EC /secured/assets/documents/en/data-sheet/P2010EC.pdf Data Sheet N 980000996212993340 2023-06-18 pdf Y en Mar 14, 2016 980000996212993340 Data Sheet N P2010 QorIQ Integrated Processor Hardware Specifications - Data Sheets 4 3 English This document describes the P2020 electrical characteristics. 1302304608307727528114 PSP 1.9 MB Registration without Disclaimer None documents Extended 1302304608307727528114 /secured/assets/documents/en/data-sheet/P2020EC.pdf 1899579 /secured/assets/documents/en/data-sheet/P2020EC.pdf P2020EC documents Y N 2016-10-31 P2020 QorIQ Integrated Processor Hardware Specifications - Data Sheets /webapp/Download?colCode=P2020EC /secured/assets/documents/en/data-sheet/P2020EC.pdf Data Sheet N 980000996212993340 2023-06-18 pdf Y en Mar 14, 2016 980000996212993340 Data Sheet N P2020 QorIQ Integrated Processor Hardware Specifications - Data Sheets Reference Manual Reference Manual 4 5 1 English This reference manual describes the resources defined for the Power ISA embedded environment. 1319210247754725815434 PSP 10.4 MB Registration without Disclaimer None documents Extended 1319210247754725815434 /secured/assets/documents/en/reference-manual/EREF_RM.pdf 10448185 /secured/assets/documents/en/reference-manual/EREF_RM.pdf EREF_RM documents Y N 2016-10-31 EREF_RM, EREF: A Programmer's Reference Manual for Freescale Power Architecture Processors - Reference Manual /webapp/Download?colCode=EREF_RM /secured/assets/documents/en/reference-manual/EREF_RM.pdf Reference Manual N 500633505221135046 2022-12-07 pdf Y en Jun 26, 2014 500633505221135046 Reference Manual Y N EREF_RM, EREF: A Programmer's Reference Manual for Freescale Power Architecture Processors - Reference Manual 6 0 English This document describes the functionality of NXP&#8217;s integrated security engine (SEC 3.1). The SEC 3.1 is designed to off-load computationally intensive security functions, such as key generation and exchange, authentication, and bulk encryption from the processor core of the SoC. 1355978300497711919636 PSP 1.2 MB Registration without Disclaimer None documents Extended 1355978300497711919636 /secured/assets/documents/en/reference-manual/P2020SEC.pdf 1218749 /secured/assets/documents/en/reference-manual/P2020SEC.pdf P2020SECRM documents Y N 2012-12-19 P2020 Security (SEC 3.1) Reference Manual /webapp/Download?colCode=P2020SECRM /secured/assets/documents/en/reference-manual/P2020SEC.pdf Reference Manual N 500633505221135046 2023-06-18 pdf Y en Dec 19, 2012 500633505221135046 Reference Manual Y N P2020 Security (SEC 3.1) Reference Manual 7 0 English Multicore devices provide a path forward for increased performance. This path requires comprehensive and pervasive system and software changes as well as new, innovative hardware designs to ensure that the software can take advantage of the increased computational power. NXP Semiconductors, Inc. has years of experience with many types of embedded multicore devices and thus can ensure that all necessary components are present to ease the software burden and to avoid having an inefficient core. This bala 1247173677125723218813 PSP 1.5 MB Registration without Disclaimer None documents Extended 1247173677125723218813 /secured/assets/documents/en/reference-manual/EMBMCRM.pdf 1486324 /secured/assets/documents/en/reference-manual/EMBMCRM.pdf EMBMCRM documents Y N 2016-10-31 Embedded Multicore: An Introduction /webapp/Download?colCode=EMBMCRM /secured/assets/documents/en/reference-manual/EMBMCRM.pdf Reference Manual N 500633505221135046 2022-12-07 pdf Y en Jul 20, 2009 500633505221135046 Reference Manual Y N Embedded Multicore: An Introduction 8 1 English The primary objective of this user&#8217;s manual is to describe the functionality of the e500 embedded microprocessor core for software and hardware developers. The e500 processor core is a low-power implementation of the family of reduced instruction set computing (RISC) embedded processors that implement the Book E definition of the PowerPC architecture. The e500 is a 32-bit implementation of the Book E architecture using the lower words in the 64-bit general-purpose registers (GPRs). 111qmdXB PSP 5.7 MB None None documents None 111qmdXB /docs/en/reference-manual/E500CORERM.pdf 5707515 /docs/en/reference-manual/E500CORERM.pdf E500CORERM documents N 2016-10-31 PowerPC ™ e500 Core Family - Reference Manual /docs/en/reference-manual/E500CORERM.pdf /docs/en/reference-manual/E500CORERM.pdf Reference Manual N 500633505221135046 2022-12-07 pdf en May 11, 2005 500633505221135046 Reference Manual N PowerPC ™ e500 Core Family - Reference Manual Application Note Application Note 30 9 3 English This document is a supplement to the SEC 2/3x reference device driver. 1224778148188710027580 PSP 1.1 MB Registration without Disclaimer None documents Extended 1224778148188710027580 /secured/assets/documents/en/application-note/AN3645.pdf 1147132 /secured/assets/documents/en/application-note/AN3645.pdf AN3645 documents Y N 2016-10-31 SEC 2/3x Descriptor Programmer’s Guide /webapp/Download?colCode=AN3645 /secured/assets/documents/en/application-note/AN3645.pdf Application Note N 645036621402383989 2023-06-18 pdf Y en Apr 28, 2017 645036621402383989 Application Note N SEC 2/3x Descriptor Programmer’s Guide 10 0 English AN5125: A device tree is a tree structure used to describe the physical hardware in a system. Each node in the tree describes the characteristics of the device being represented. The purpose of the device tree is to describe device information in a system that cannot necessarily be dynamically detected or discovered by a client program. 1441302193437732651194 PSP 566.4 KB None None documents None 1441302193437732651194 /docs/en/application-note/AN5125.pdf 566365 /docs/en/application-note/AN5125.pdf AN5125 documents N N 2016-10-31 AN5125, Introduction to Device Trees - Application Note /docs/en/application-note/AN5125.pdf /docs/en/application-note/AN5125.pdf Application Note N 645036621402383989 2022-12-07 pdf N en Sep 3, 2015 645036621402383989 Application Note Y N AN5125, Introduction to Device Trees - Application Note 11 4 English AN4039: This application note expands on the description of the double data rate (DDR3) memory controller programmable registers in the PowerQUICC<sup>&#174;</sup> and QorIQ<sup>&#174;</sup> processor reference manuals. 1264810112254717714233 PSP 468.7 KB None None documents None 1264810112254717714233 /docs/en/application-note/AN4039.pdf 468655 /docs/en/application-note/AN4039.pdf AN4039 documents N N 2016-10-31 AN4039, PowerQUICC and QorIQ DDR3 SDRAM Controller Register Setting Considerations - Application Note /docs/en/application-note/AN4039.pdf /docs/en/application-note/AN4039.pdf Application Note N 645036621402383989 2022-12-07 pdf N en Nov 11, 2014 645036621402383989 Application Note N AN4039, PowerQUICC and QorIQ DDR3 SDRAM Controller Register Setting Considerations - Application Note 12 4 English AN4261: This document provides recommendations for new designs based on the P2020 QorIQ<sup>&#174;</sup> integrated processor. 1302304510802709851940 PSP 453.1 KB Registration without Disclaimer None documents Extended 1302304510802709851940 /secured/assets/documents/en/application-note/AN4261.pdf 453077 /secured/assets/documents/en/application-note/AN4261.pdf AN4261 documents Y N 2016-10-31 AN4261, P2020 QorIQ Integrated Processor Design Checklist - Application Note /webapp/Download?colCode=AN4261 /secured/assets/documents/en/application-note/AN4261.pdf Application Note N 645036621402383989 2022-12-07 pdf Y en Apr 24, 2014 645036621402383989 Application Note N AN4261, P2020 QorIQ Integrated Processor Design Checklist - Application Note 13 4 English AN4309: This document provides recommendations for new designs based on the P2010 QorIQ<sup>&#174;</sup> integrated processor. 1302304507235733638638 PSP 452.4 KB Registration without Disclaimer None documents Extended 1302304507235733638638 /secured/assets/documents/en/application-note/AN4309.pdf 452355 /secured/assets/documents/en/application-note/AN4309.pdf AN4309 documents Y N 2016-10-31 AN4309, P2010 QorIQ Integrated Processor Design Checklist - Application Note /webapp/Download?colCode=AN4309 /secured/assets/documents/en/application-note/AN4309.pdf Application Note N 645036621402383989 2022-12-07 pdf Y en Apr 24, 2014 645036621402383989 Application Note N AN4309, P2010 QorIQ Integrated Processor Design Checklist - Application Note 14 0 English AN4848: The PCIe bus has been gaining popularity over the last decade. Almost all of Our mid and high-end devices offer at least one PCIe port as part of their standard SOC. Most of them offer more than a single port, thus eliminating the need for an external PCIe switch. 1390372586014711432307 PSP 1.2 MB Registration without Disclaimer None documents Extended 1390372586014711432307 /secured/assets/documents/en/application-note/AN4848.pdf 1207848 /secured/assets/documents/en/application-note/AN4848.pdf AN4848 documents Y N 2016-10-31 AN4848, Simple Program to Confirm PCIe Connectivity - Application Notes /webapp/Download?colCode=AN4848 /secured/assets/documents/en/application-note/AN4848.pdf Application Note N 645036621402383989 2023-06-18 pdf Y en Jan 21, 2014 645036621402383989 Application Note N AN4848, Simple Program to Confirm PCIe Connectivity - Application Notes 15 2 English This document describes the requirements and step-by-step procedures for forcing the DRAM into self-refresh mode. 1363012931515701443659 PSP 269.4 KB None None documents None 1363012931515701443659 /docs/en/application-note/AN4531.pdf 269380 /docs/en/application-note/AN4531.pdf AN4531 documents N N 2016-10-31 AN4531, Achieving Persistent DRAM on PowerQUICC III and QorIQ Processors - Application Notes /docs/en/application-note/AN4531.pdf /docs/en/application-note/AN4531.pdf Application Note N 645036621402383989 2022-12-07 pdf N en Dec 16, 2013 645036621402383989 Application Note N AN4531, Achieving Persistent DRAM on PowerQUICC III and QorIQ Processors - Application Notes 16 6 English AN3940: This document provides general hardware and layout considerations and guidelines for hardware engineers implementing a DDR3 memory subsystem. 1264793052715706871063 PSP 547.7 KB Registration without Disclaimer None documents Extended 1264793052715706871063 /secured/assets/documents/en/application-note/AN3940.pdf 547662 /secured/assets/documents/en/application-note/AN3940.pdf AN3940 documents Y N 2016-10-31 AN3940, Hardware and Layout Design Considerations for DDR3 SDRAM Memory Interfaces - App Note /webapp/Download?colCode=AN3940 /secured/assets/documents/en/application-note/AN3940.pdf Application Note N 645036621402383989 2023-06-18 pdf Y en Nov 25, 2013 645036621402383989 Application Note Y N AN3940, Hardware and Layout Design Considerations for DDR3 SDRAM Memory Interfaces - App Note 17 1 English This document describes how to calculate the maximum frequency and transfer formats and includes eSPI programming examples. 1329517560294722281831 PSP 216.6 KB None None documents None 1329517560294722281831 /docs/en/application-note/AN4375.pdf 216552 /docs/en/application-note/AN4375.pdf AN4375 documents N N 2016-10-31 QorIQ eSPI Controller Register Setting Considerations and Programming Examples /docs/en/application-note/AN4375.pdf /docs/en/application-note/AN4375.pdf Application Note N 645036621402383989 2022-12-07 pdf N en Jun 21, 2012 645036621402383989 Application Note N QorIQ eSPI Controller Register Setting Considerations and Programming Examples 18 2 English This document describes on-chip ROM booting from an SD card/MMC or from an EEPROM under a Linux&#13;&#10;operating system. 1229718093838710459075 PSP 334.2 KB None None documents None 1229718093838710459075 /docs/en/application-note/AN3659.pdf 334243 /docs/en/application-note/AN3659.pdf AN3659 documents N N 2016-10-31 Booting from On-Chip ROM (eSDHC or eSPI) /docs/en/application-note/AN3659.pdf /docs/en/application-note/AN3659.pdf Application Note N 645036621402383989 2022-12-07 pdf N en Jun 15, 2012 645036621402383989 Application Note N Booting from On-Chip ROM (eSDHC or eSPI) 19 0 English This application note describes a procedure that allows users to validate the implementation of 1588-specific hardware in their system. 1309961595210675753552 PSP 743.2 KB None None documents None 1309961595210675753552 /docs/en/application-note/AN4326.pdf 743199 /docs/en/application-note/AN4326.pdf AN4326 documents N 2016-10-31 Verification of the IEEE 1588 Interface /docs/en/application-note/AN4326.pdf /docs/en/application-note/AN4326.pdf Application Note N 645036621402383989 2022-12-07 pdf en Jul 6, 2011 645036621402383989 Application Note N Verification of the IEEE 1588 Interface 20 Rev. 0 English This application note describes some reference connection schemes when interfacing the third-party clock driver chip&#8217;s output with the SerDes Reference Clock inputs of PowerQUICC<sup>&#174;</sup> or QorIQ<sup>&#174;</sup> devices. It also summarizes some recommendations for PCI Express and SRIO HSSI measurement. 1305312143395731535528 PSP 577.2 KB Registration without Disclaimer None documents Extended 1305312143395731535528 /secured/assets/documents/en/application-note/AN4311.pdf 577164 /secured/assets/documents/en/application-note/AN4311.pdf AN4311 documents Y N 2016-10-31 SerDes Reference Clock Interfacing and HSSI Measurements Recommendations /webapp/Download?colCode=AN4311 /secured/assets/documents/en/application-note/AN4311.pdf Application Note N 645036621402383989 2023-06-18 pdf Y en May 13, 2011 645036621402383989 Application Note Y N SerDes Reference Clock Interfacing and HSSI Measurements Recommendations 21 0 English 1287581868481730872047 PSP 142.0 KB None None documents None 1287581868481730872047 /docs/en/application-note/AN3423.pdf 141965 /docs/en/application-note/AN3423.pdf AN3423 documents N 2016-10-31 Support for IEEE 1588™ Protocol in PowerQUICC and QorIQ Processors /docs/en/application-note/AN3423.pdf /docs/en/application-note/AN3423.pdf Application Note N 645036621402383989 2022-12-07 pdf en Oct 6, 2010 645036621402383989 Application Note N Support for IEEE 1588™ Protocol in PowerQUICC and QorIQ Processors 22 1 English This application note describes how to use and benefit from DDR memory interleaving. 1251150824863717930878 PSP 717.3 KB Registration without Disclaimer None documents Extended 1251150824863717930878 /secured/assets/documents/en/application-note/AN3939.pdf 717276 /secured/assets/documents/en/application-note/AN3939.pdf AN3939 documents Y N 2016-10-31 DDR Interleaving for PowerQUICC and QorIQ Processors /webapp/Download?colCode=AN3939 /secured/assets/documents/en/application-note/AN3939.pdf Application Note N 645036621402383989 2022-12-07 pdf Y en Jun 30, 2010 645036621402383989 Application Note Y N DDR Interleaving for PowerQUICC and QorIQ Processors 23 0 English AN4064: This document explains how to enable and utilize 36-bit physical addressing. It describes the 36-bit capabilities of the e600 and e500v2, and later processor families. Addressing and memory management in a computer system is a difficult topic that is largely beyond the scope of this document. This section explains some of the basic concepts that are essential to understand in order to develop system-level software that utilizes 36-bit physical addressing. 1269842191514722596708 PSP 576.8 KB None None documents None 1269842191514722596708 /docs/en/application-note/AN4064.pdf 576818 /docs/en/application-note/AN4064.pdf AN4064 documents N 2016-10-31 AN4064, Utilizing 36-Bit Physical Addressing in U-Boot and Linux - Application Notes /docs/en/application-note/AN4064.pdf /docs/en/application-note/AN4064.pdf Application Note N 645036621402383989 2022-12-07 pdf en Mar 28, 2010 645036621402383989 Application Note N AN4064, Utilizing 36-Bit Physical Addressing in U-Boot and Linux - Application Notes 24 1 English This application note describes basic jitter terminology and the aspects pertaining to the SYSCLK clock design requirements. 1264143083962735811350 PSP 514.4 KB None None documents None 1264143083962735811350 /docs/en/application-note/AN4056.pdf 514364 /docs/en/application-note/AN4056.pdf AN4056 documents N 2016-10-31 Understanding SYSCLK Jitter /docs/en/application-note/AN4056.pdf /docs/en/application-note/AN4056.pdf Application Note N 645036621402383989 2022-12-07 pdf en Feb 18, 2010 645036621402383989 Application Note N Understanding SYSCLK Jitter 25 2 English NXP Semiconductors Power Architecture&#8482;&#13;&#10;technology-based evaluation and development platforms may optionally implement a &#8220;System ID&#8221; non-volatile memory device. This device stores important configuration data about the board. 1213738938672737755656 PSP 495.3 KB None None documents None 1213738938672737755656 /docs/en/application-note/AN3638.pdf 495318 /docs/en/application-note/AN3638.pdf AN3638 documents N N 2016-10-31 The SystemID Format for Power Architecture™ Development Systems /docs/en/application-note/AN3638.pdf /docs/en/application-note/AN3638.pdf Application Note N 645036621402383989 2022-12-07 pdf N en Oct 26, 2009 645036621402383989 Application Note N The SystemID Format for Power Architecture™ Development Systems 26 0 English This document is an overview of how to configure&#13;&#10;PowerQUICC<sup>&#174;</sup> III and QorIQ<sup>&#174;</sup> P1xx/P2xx devices to boot from serial RapidIO&#8482; or PCI Express&#8482; with no additional boot flash/EEPROM. 1256145464773713684480 PSP 543.1 KB Registration without Disclaimer None documents Extended 1256145464773713684480 /secured/assets/documents/en/application-note/AN3646.pdf 543108 /secured/assets/documents/en/application-note/AN3646.pdf AN3646 documents Y N 2016-10-31 Booting from Serial RapidIO™/PCI Express™ on PowerQUICC™ III and QorIQ™ P1xx/P2xx /webapp/Download?colCode=AN3646 /secured/assets/documents/en/application-note/AN3646.pdf Application Note N 645036621402383989 2022-12-07 pdf Y en Oct 21, 2009 645036621402383989 Application Note N Booting from Serial RapidIO™/PCI Express™ on PowerQUICC™ III and QorIQ™ P1xx/P2xx 27 1 English Application Note 1060017730134725666689 PSP 612.9 KB None None documents None 1060017730134725666689 /docs/en/application-note/AN2490.pdf 612895 /docs/en/application-note/AN2490.pdf AN2490 documents N 2016-10-31 MPC603e and e500 Register Model Comparison /docs/en/application-note/AN2490.pdf /docs/en/application-note/AN2490.pdf Application Note N 645036621402383989 2022-12-07 pdf en Sep 23, 2009 645036621402383989 Application Note N MPC603e and e500 Register Model Comparison 28 0 English This application note explains configuration&#13;&#10;requirements to assist users to successfully program and set up this interface type. It also compares SGMII to other gigabit Ethernet standards and interfaces. 1244236817778728476903 PSP 692.4 KB Registration without Disclaimer None documents Extended 1244236817778728476903 /secured/assets/documents/en/application-note/AN3869.pdf 692438 /secured/assets/documents/en/application-note/AN3869.pdf AN3869 documents Y N 2016-10-31 Implementing SGMII Interfaces on the PowerQUICC™ III /webapp/Download?colCode=AN3869 /secured/assets/documents/en/application-note/AN3869.pdf Application Note N 645036621402383989 2022-12-07 pdf Y en Jun 5, 2009 645036621402383989 Application Note N Implementing SGMII Interfaces on the PowerQUICC™ III 29 5 English This document explains how the frequency divider to calculate the SCL speed of the I2C interface is determined for the MPC824x, MPC83xx, MPC85xx, and MPC86xx devices. 1119553728324723212395 PSP 611.4 KB Registration without Disclaimer None documents Extended 1119553728324723212395 /secured/assets/documents/en/application-note/AN2919.pdf 611358 /secured/assets/documents/en/application-note/AN2919.pdf AN2919 documents Y N 2016-10-31 Determining the I2C Frequency Divider Ratio for SCL /webapp/Download?colCode=AN2919 /secured/assets/documents/en/application-note/AN2919.pdf Application Note N 645036621402383989 2022-12-07 pdf Y en Dec 31, 2008 645036621402383989 Application Note N Determining the I2C Frequency Divider Ratio for SCL 30 0 English AN3542: This application note discusses the differences between SMP and AMP (asymmetric multi-processor) OSs, booting options and features of the MPC8572E, and configuration of shared and non-shared resources between cores. This application note also provides a description of the boot process implemented by Uboot and Linux that is provided as part of the MPC8572E development system board support package. 1202329207598722883383 PSP 519.9 KB None None documents None 1202329207598722883383 /docs/en/application-note/AN3542.pdf 519909 /docs/en/application-note/AN3542.pdf AN3542 documents N 2016-10-31 AN3542, SMP Boot Process for Dual E500 Cores - Application Notes /docs/en/application-note/AN3542.pdf /docs/en/application-note/AN3542.pdf Application Note N 645036621402383989 2022-12-07 pdf en Jan 25, 2008 645036621402383989 Application Note N AN3542, SMP Boot Process for Dual E500 Cores - Application Notes 31 0 English This application note provides an overview and specific strategies for cache coherency and potential performance impacts in the PowerQUICC<sup>&#174;</sup> II Pro and PowerQUICC III families. It focuses on data coherency and potential system issues, as well as some concerns associated with having multiple DMA devices. It also discusses the specific steps and interdependencies required to implement hardware enforced cache coherency. 1198270786976715604383 PSP 547.7 KB None None documents None 1198270786976715604383 /docs/en/application-note/AN3544.pdf 547694 /docs/en/application-note/AN3544.pdf AN3544 documents N 2016-10-31 PowerQUICC™ Data Cache Coherency /docs/en/application-note/AN3544.pdf /docs/en/application-note/AN3544.pdf Application Note N 645036621402383989 2022-12-07 pdf en Dec 21, 2007 645036621402383989 Application Note N PowerQUICC™ Data Cache Coherency 32 1 English This document describes aspects of memory synchronization and cache coherency requirements for NXP&#8217;s PowerQUICC<sup>&#174;</sup>&#8482; III product family. Coherency and synchronization need be considered, both for data and instructions, when initializing memory or moving memory contents from one location to another. 1191253168152709402147 PSP 189.0 KB None None documents None 1191253168152709402147 /docs/en/application-note/AN3441.pdf 188954 /docs/en/application-note/AN3441.pdf AN3441 documents N 2016-10-31 Coherency and Synchronization Requirements for PowerQUICC™ III /docs/en/application-note/AN3441.pdf /docs/en/application-note/AN3441.pdf Application Note N 645036621402383989 2022-12-07 pdf en Dec 17, 2007 645036621402383989 Application Note N Coherency and Synchronization Requirements for PowerQUICC™ III 33 1 English The enhanced three-speed Ethernet controller (eTSEC) offered on many PowerQUICC&#8482; II Pro, PowerQUICC&#8482; III, and other devices, allows for flexible manipulation of incoming and outgoing Ethernet data. One such feature is the ability to receive and propagate padded, or &#8220;shimmed,&#8221; OSI layer 2 data to accommodate custom routing or direction of Ethernet data within a network. This application note describes what the shimming functionality does and the details of how to best utilize it. 1196114880779719950774 PSP 497.2 KB None None documents None 1196114880779719950774 /docs/en/application-note/AN3537.pdf 497175 /docs/en/application-note/AN3537.pdf AN3537 documents N 2016-10-31 Accommodating Layer 2 Padding (Shimming) with the Enhanced Three-Speed Ethernet Controller (eTSEC) /docs/en/application-note/AN3537.pdf /docs/en/application-note/AN3537.pdf Application Note N 645036621402383989 2022-12-07 pdf en Dec 6, 2007 645036621402383989 Application Note N Accommodating Layer 2 Padding (Shimming) with the Enhanced Three-Speed Ethernet Controller (eTSEC) 34 0 English This application note provides an introduction to the error correcting code (ECC) technology as well as an aid to initialization and error recovery on Our PowerQUICC<sup>&#174;</sup> III family of processors. 1196228463425717224884 PSP 573.0 KB None None documents None 1196228463425717224884 /docs/en/application-note/AN3532.pdf 572952 /docs/en/application-note/AN3532.pdf AN3532 documents N 2016-10-31 Error Correction and Error Handling on PowerQUICC (TM) III Processors /docs/en/application-note/AN3532.pdf /docs/en/application-note/AN3532.pdf Application Note N 645036621402383989 2022-12-07 pdf en Nov 27, 2007 645036621402383989 Application Note N Error Correction and Error Handling on PowerQUICC (TM) III Processors 35 0 English AN3445: This application note outlines general, high-level, architectural differences between the e300 and e500 family processors. The e300 family (which are based on the original 603 design) was designed to the original PowerPC architecture definition. The e500v1 and e500v2 processors are designed to what was originally the PowerPC Book E architecture and NXP?s embedded implementation standards (EIS). 1194389310604697206738 PSP 935.0 KB None None documents None 1194389310604697206738 /docs/en/application-note/AN3445.pdf 934951 /docs/en/application-note/AN3445.pdf AN3445 documents N 2016-10-31 AN3445, Migrating from e300- to e500-Based Integrated Devices - Application Notes /docs/en/application-note/AN3445.pdf /docs/en/application-note/AN3445.pdf Application Note N 645036621402383989 2022-12-07 pdf en Oct 31, 2007 645036621402383989 Application Note N AN3445, Migrating from e300- to e500-Based Integrated Devices - Application Notes 36 0 English AN3531: This application note outlines general, high-level, architectural differences between the e600 and e500 family processors. Is intended as a general guideline for programmers and system designers who are assessing the efforts required in migrating to e500-based devices. 1194389312415718217914 PSP 961.6 KB None None documents None 1194389312415718217914 /docs/en/application-note/AN3531.pdf 961596 /docs/en/application-note/AN3531.pdf AN3531 documents N N 2016-10-31 AN3531, Migrating from e600- to e500-Based Integrated Devices - Application Notes /docs/en/application-note/AN3531.pdf /docs/en/application-note/AN3531.pdf Application Note N 645036621402383989 2022-12-07 pdf N en Oct 31, 2007 645036621402383989 Application Note N AN3531, Migrating from e600- to e500-Based Integrated Devices - Application Notes 37 2 English These design guidelines are applicable for products that leverage the DDR2 SDRAM IP core, and are based on a compilation of internal platforms designed by NXP Semiconductors, Inc. These guidelines are constructed in such a fashion as to minimize board-related issues across multiple memory topologies while allowing maximum flexibility for the board designer. 1128961595061725581551 PSP 619.7 KB None None documents None 1128961595061725581551 /docs/en/application-note/AN2910.pdf 619650 /docs/en/application-note/AN2910.pdf AN2910 documents N 2016-10-31 Hardware and Layout Design Considerations for DDR2 SDRAM Memory Interfaces /docs/en/application-note/AN2910.pdf /docs/en/application-note/AN2910.pdf Application Note N 645036621402383989 2022-12-07 pdf en Mar 27, 2007 645036621402383989 Application Note N Hardware and Layout Design Considerations for DDR2 SDRAM Memory Interfaces 38 0 English AN2665: This application note provides information to programmers so that they may write optimal code for the PowerPC ? e500 embedded microprocessor cores. The e500 core implements the Book E version of the PowerPC architecture. In addition, the e500 core adheres to the NXP Book E implementation standards (EIS). These standards were developed to ensure consistency among NXP?s Book E implementations. 1112972998032717039588 PSP 799.6 KB None None documents None 1112972998032717039588 /docs/en/application-note/AN2665.pdf 799625 /docs/en/application-note/AN2665.pdf AN2665 documents N 2016-10-31 AN2665, e500 Software Optimization Guide (eSOG) - Application Notes /docs/en/application-note/AN2665.pdf /docs/en/application-note/AN2665.pdf Application Note N 645036621402383989 2022-12-07 pdf en Apr 8, 2005 645036621402383989 Application Note N AN2665, e500 Software Optimization Guide (eSOG) - Application Notes User Guide User Guide 1 39 1 Y English https://docs.nxp.com/bundle/GUID-805CC0EA-4001-47AD-86CD-4F340751F6B7/page/GUID-17B5D04F-6471-4EC6-BEB9-DE4D0AFA034A.html Y 1576719019599707128294 PSP None None documents None 1576719019599707128294 /docs/en/user-guide/SPECTRE-MELTDOWN-POWER-ISA-DOC /docs/en/user-guide/SPECTRE-MELTDOWN-POWER-ISA-DOC SPECTRE-MELTDOWN-POWER-ISA-DOC documents N N Y 2019-12-18 Spectre and Meltdown Updates for Power ISA Cores https://docs.nxp.com/bundle/GUID-805CC0EA-4001-47AD-86CD-4F340751F6B7/page/GUID-17B5D04F-6471-4EC6-BEB9-DE4D0AFA034A.html /docs/en/user-guide/SPECTRE-MELTDOWN-POWER-ISA-DOC User Guide N 132339537837198660 Y /bundle/GUID-805CC0EA-4001-47AD-86CD-4F340751F6B7/page/GUID-17B5D04F-6471-4EC6-BEB9-DE4D0AFA034A.html 2022-12-07 N en Nov 14, 2019 132339537837198660 User Guide Y N Spectre and Meltdown Updates for Power ISA Cores Application Note Software Application Note Software 1 40 0 English This application note addresses a common challenge encountered during circuit board testing with some of the newer NXP microprocessors. It is common practice for board testing houses to test for shorts on the power rails by measuring the resistance from a power rail to the ground rail. In older technologies, this is a reasonable approach. However, this application note explains why this approach can be problematic when used with devices in newer technologies. 1181767584945705509512 PSP 163.7 KB None None documents None 1181767584945705509512 /docs/en/application-note-software/AN3372.pdf 163681 /docs/en/application-note-software/AN3372.pdf AN3372 documents N 2016-10-31 Challenges in Testing for Power Rail Shorts with New Technologies /docs/en/application-note-software/AN3372.pdf /docs/en/application-note-software/AN3372.pdf Application Note Software N 789425793691620447 2022-12-07 pdf en Jun 13, 2007 789425793691620447 Application Note Software N Challenges in Testing for Power Rail Shorts with New Technologies Brochure Brochure 1 41 0 English QorIQ<sup>&#174;</sup> communications processors are the next-generation evolution of our leading PowerQUICC<sup>&#174;</sup> &#174; communications processors. Based on high-performance e500 cores built on Power Architecture &#174; technology. The QorIQ P2 platform series, which includes the P2020 and P2010 communications processors, delivers unprecedented performance per watt. The series delivers dual- and single-core frequencies from 800 MHz to 1.2 GHz. 1244825988989716147424 PSP 4.1 MB None None documents None 1244825988989716147424 /docs/en/brochure/P2_Family_App_Bro.pdf 4070334 /docs/en/brochure/P2_Family_App_Bro.pdf P2_FAMILY_APP_BRO documents N 2016-10-31 QorIQ P2 Family Communications Processors - Application Brief /docs/en/brochure/P2_Family_App_Bro.pdf /docs/en/brochure/P2_Family_App_Bro.pdf Brochure N 712453003803778552 2022-12-07 pdf en Jun 12, 2009 712453003803778552 Brochure N QorIQ P2 Family Communications Processors - Application Brief Technical Notes Technical Notes 1 42 0 English Provides a COMe pin-out for QorIQ<sup>&#174;</sup> devices 1299186935006725024525 PSP 492.6 KB Registration without Disclaimer None documents Extended 1299186935006725024525 /secured/assets/documents/en/engineering-bulletin/EB739.pdf 492591 /secured/assets/documents/en/engineering-bulletin/EB739.pdf EB739 documents Y N 2016-10-31 COM Express Pin Assignments for QorIQ Devices /webapp/Download?colCode=EB739 /secured/assets/documents/en/engineering-bulletin/EB739.pdf Technical Notes N 389245547230346745 2022-12-07 pdf Y en Mar 3, 2011 389245547230346745 Technical Notes N COM Express Pin Assignments for QorIQ Devices Fact Sheet Fact Sheet 4 43 1 English NXP&#8217;s UTM and security appliance solution exemplifies our solutions-centric approach by bringing together all three elements needed for the development of a complete UTM security appliance: processors, software and an ecosystem of hardware and software partners, providing our customers a complete solution to deliver differentiated products to market. 1267326981318733118436 PSP 969.1 KB None None documents None 1267326981318733118436 /docs/en/fact-sheet/P2020UTMAPPFS.pdf 969061 /docs/en/fact-sheet/P2020UTMAPPFS.pdf P2020UTMAPPFS documents N N 2016-10-31 QorIQ™ P2020 UTM/Security Appliance Solution /docs/en/fact-sheet/P2020UTMAPPFS.pdf /docs/en/fact-sheet/P2020UTMAPPFS.pdf Fact Sheet N 736675474163315314 2022-12-07 pdf N en Feb 14, 2020 736675474163315314 Fact Sheet Y N QorIQ™ P2020 UTM/Security Appliance Solution 44 2 English 1192384455671724743414 PSP 441.8 KB None None documents None 1192384455671724743414 /docs/en/fact-sheet/LTEWIMAXFS.pdf 441802 /docs/en/fact-sheet/LTEWIMAXFS.pdf LTEWIMAXFS documents N 2016-10-31 Modular AdvancedMC Platform for Broadband/LTE Base Stations Fact Sheet /docs/en/fact-sheet/LTEWIMAXFS.pdf /docs/en/fact-sheet/LTEWIMAXFS.pdf Fact Sheet N 736675474163315314 2022-12-07 pdf en Feb 19, 2010 736675474163315314 Fact Sheet N Modular AdvancedMC Platform for Broadband/LTE Base Stations Fact Sheet 45 v4 English 1244223699499702220156 PSP 304.7 KB None None documents None 1244223699499702220156 /docs/en/fact-sheet/P2020DS.pdf 304717 /docs/en/fact-sheet/P2020DS.pdf P2020DS documents N 2016-10-31 P2020 Development System /docs/en/fact-sheet/P2020DS.pdf /docs/en/fact-sheet/P2020DS.pdf Fact Sheet N 736675474163315314 2022-12-07 pdf en Jun 5, 2009 736675474163315314 Fact Sheet N P2020 Development System 46 v4 English 1244223699965708466197 PSP 447.2 KB None None documents None 1244223699965708466197 /docs/en/fact-sheet/P2020RDB.pdf 447187 /docs/en/fact-sheet/P2020RDB.pdf P2020RDB documents N 2016-10-31 P2020 Reference Design Board /docs/en/fact-sheet/P2020RDB.pdf /docs/en/fact-sheet/P2020RDB.pdf Fact Sheet N 736675474163315314 2022-12-07 pdf en Jun 5, 2009 736675474163315314 Fact Sheet N P2020 Reference Design Board Product Brief Product Brief 1 47 1 English This document provides an overview of features and functionality of the P2020 and P2010 QorIQ<sup>&#174;</sup> communications processors. 1232486626815740001812 PSP 206.0 KB Registration without Disclaimer None documents Extended 1232486626815740001812 /secured/assets/documents/en/product-brief/P2020PB.pdf 206013 /secured/assets/documents/en/product-brief/P2020PB.pdf P2020PB documents Y N 2016-10-31 P2020/P2010 QorIQ Communications Processor Product Brief /webapp/Download?colCode=P2020PB /secured/assets/documents/en/product-brief/P2020PB.pdf Product Brief N 899114358132306053 2022-12-07 pdf Y en Jun 22, 2012 899114358132306053 Product Brief N P2020/P2010 QorIQ Communications Processor Product Brief Supporting Information Supporting Information 2 48 1.9 English FSLNISTCAVP: NXP<sup>&#174;</sup> Semiconductors has performed NIST CAVP testing of cryptographic accelerators (called Execution Units or EUs) found in multiple product families, including the PowerQUICC<sup>&#174;</sup> and QorIQ<sup>&#174;</sup> embedded communications processors, and the StarCore<sup>&#174;</sup> digital signal processors. 1368836090577704535160 PSP 303.5 KB None None documents None 1368836090577704535160 /docs/en/supporting-information/FSLNISTCAVP.pdf 303546 /docs/en/supporting-information/FSLNISTCAVP.pdf FSLNISTCAVP documents N N 2016-11-09 FSLNISTCAVP, NIST Crypto Algorithm Validation Program Certifications for NXP<sup>®</sup> Cryptographic Accelerators - White Paper /docs/en/supporting-information/FSLNISTCAVP.pdf /docs/en/supporting-information/FSLNISTCAVP.pdf Supporting Information N 371282830530968666 2022-12-07 pdf N en Oct 28, 2016 371282830530968666 Supporting Information Y N FSLNISTCAVP, NIST Crypto Algorithm Validation Program Certifications for NXP<sup>®</sup> Cryptographic Accelerators - White Paper 49 2 English Customer Export Control Information Document 1232680174357742940244 PSP 158.4 KB None None documents None 1232680174357742940244 /docs/en/supporting-information/P2020FAMPECI.pdf 158367 /docs/en/supporting-information/P2020FAMPECI.pdf P2020FAMPECI documents N N 2016-10-31 P2020 Family Customer Export Control Information /docs/en/supporting-information/P2020FAMPECI.pdf /docs/en/supporting-information/P2020FAMPECI.pdf Supporting Information N 371282830530968666 2023-06-19 pdf N en Dec 10, 2010 371282830530968666 Supporting Information Y N P2020 Family Customer Export Control Information White Paper White Paper 3 50 0 English In this paper, we present the mitigations for Spectre variant 1 and Spectre variant 2 for NXP PowerPC processors. The NXP PowerPC processors are not vulnerable to the Meltdown attack, Spectre variant 1.1/1.2, or Spectre variant 4. 1580452712610724357770 PSP 317.1 KB None None documents None 1580452712610724357770 /docs/en/white-paper/SPECTREPPCWP.pdf 317053 /docs/en/white-paper/SPECTREPPCWP.pdf SPECTREPPCWP documents N N 2020-01-30 Speculative Execution Vulnerabilities and Mitigations on NXP PowerPC Processors White Paper /docs/en/white-paper/SPECTREPPCWP.pdf /docs/en/white-paper/SPECTREPPCWP.pdf White Paper N 918633085541740938 2022-12-07 pdf N en Jan 30, 2020 918633085541740938 White Paper Y N Speculative Execution Vulnerabilities and Mitigations on NXP PowerPC Processors White Paper 51 0 English CritialBlue&#13;&#10;&#13;&#10;Prism software 1289917463417712987902 PSP 673.1 KB None None documents None 1289917463417712987902 /docs/en/white-paper/LTEWHTPPRCRTBLA4.pdf 673125 /docs/en/white-paper/LTEWHTPPRCRTBLA4.pdf LTEWHTPPRCRTBLA4 documents N 2016-10-31 Tuning QorIQ Processor Performance /docs/en/white-paper/LTEWHTPPRCRTBLA4.pdf /docs/en/white-paper/LTEWHTPPRCRTBLA4.pdf White Paper N 918633085541740938 2022-12-07 pdf en Nov 16, 2010 918633085541740938 White Paper N Tuning QorIQ Processor Performance 52 3 English Network security protocols and applications use a variety of cryptographic algorithms to achieve these high-level goals. Because cryptography is computationally intensive, hardware acceleration is highly desirable when cryptographic algorithms are frequent system functions. 1227561595497709456436 PSP 580.1 KB Registration without Disclaimer None documents Extended 1227561595497709456436 /secured/assets/documents/en/white-paper/CRYPTOWP.pdf 580121 /secured/assets/documents/en/white-paper/CRYPTOWP.pdf CRYPTOWP documents Y N 2016-10-31 Understanding Cryptographic Performance /webapp/Download?colCode=CRYPTOWP /secured/assets/documents/en/white-paper/CRYPTOWP.pdf White Paper N 918633085541740938 2022-12-07 pdf Y en Aug 15, 2008 918633085541740938 White Paper Y N Understanding Cryptographic Performance false 0 P2020 downloads en true 1 Y PSP Application Note 30 /secured/assets/documents/en/application-note/AN3645.pdf 2016-10-31 1224778148188710027580 PSP 9 Apr 28, 2017 Application Note This document is a supplement to the SEC 2/3x reference device driver. Registration without Disclaimer /secured/assets/documents/en/application-note/AN3645.pdf English documents 1147132 None 645036621402383989 2023-06-18 Y /webapp/Download?colCode=AN3645 SEC 2/3x Descriptor Programmer’s Guide /secured/assets/documents/en/application-note/AN3645.pdf documents 645036621402383989 Application Note N en Extended pdf 3 Y N SEC 2/3x Descriptor Programmer’s Guide 1.1 MB AN3645 N 1224778148188710027580 /docs/en/application-note/AN5125.pdf 2016-10-31 1441302193437732651194 PSP 10 Sep 3, 2015 Application Note AN5125: A device tree is a tree structure used to describe the physical hardware in a system. Each node in the tree describes the characteristics of the device being represented. The purpose of the device tree is to describe device information in a system that cannot necessarily be dynamically detected or discovered by a client program. None /docs/en/application-note/AN5125.pdf English documents 566365 None 645036621402383989 2022-12-07 N /docs/en/application-note/AN5125.pdf AN5125, Introduction to Device Trees - Application Note /docs/en/application-note/AN5125.pdf documents 645036621402383989 Application Note N en None Y pdf 0 N N AN5125, Introduction to Device Trees - Application Note 566.4 KB AN5125 N 1441302193437732651194 /docs/en/application-note/AN4039.pdf 2016-10-31 1264810112254717714233 PSP 11 Nov 11, 2014 Application Note AN4039: This application note expands on the description of the double data rate (DDR3) memory controller programmable registers in the PowerQUICC<sup>&#174;</sup> and QorIQ<sup>&#174;</sup> processor reference manuals. None /docs/en/application-note/AN4039.pdf English documents 468655 None 645036621402383989 2022-12-07 N /docs/en/application-note/AN4039.pdf AN4039, PowerQUICC and QorIQ DDR3 SDRAM Controller Register Setting Considerations - Application Note /docs/en/application-note/AN4039.pdf documents 645036621402383989 Application Note N en None pdf 4 N N AN4039, PowerQUICC and QorIQ DDR3 SDRAM Controller Register Setting Considerations - Application Note 468.7 KB AN4039 N 1264810112254717714233 /secured/assets/documents/en/application-note/AN4261.pdf 2016-10-31 1302304510802709851940 PSP 12 Apr 24, 2014 Application Note AN4261: This document provides recommendations for new designs based on the P2020 QorIQ<sup>&#174;</sup> integrated processor. Registration without Disclaimer /secured/assets/documents/en/application-note/AN4261.pdf English documents 453077 None 645036621402383989 2022-12-07 Y /webapp/Download?colCode=AN4261 AN4261, P2020 QorIQ Integrated Processor Design Checklist - Application Note /secured/assets/documents/en/application-note/AN4261.pdf documents 645036621402383989 Application Note N en Extended pdf 4 Y N AN4261, P2020 QorIQ Integrated Processor Design Checklist - Application Note 453.1 KB AN4261 N 1302304510802709851940 /secured/assets/documents/en/application-note/AN4309.pdf 2016-10-31 1302304507235733638638 PSP 13 Apr 24, 2014 Application Note AN4309: This document provides recommendations for new designs based on the P2010 QorIQ<sup>&#174;</sup> integrated processor. Registration without Disclaimer /secured/assets/documents/en/application-note/AN4309.pdf English documents 452355 None 645036621402383989 2022-12-07 Y /webapp/Download?colCode=AN4309 AN4309, P2010 QorIQ Integrated Processor Design Checklist - Application Note /secured/assets/documents/en/application-note/AN4309.pdf documents 645036621402383989 Application Note N en Extended pdf 4 Y N AN4309, P2010 QorIQ Integrated Processor Design Checklist - Application Note 452.4 KB AN4309 N 1302304507235733638638 /secured/assets/documents/en/application-note/AN4848.pdf 2016-10-31 1390372586014711432307 PSP 14 Jan 21, 2014 Application Note AN4848: The PCIe bus has been gaining popularity over the last decade. Almost all of Our mid and high-end devices offer at least one PCIe port as part of their standard SOC. Most of them offer more than a single port, thus eliminating the need for an external PCIe switch. Registration without Disclaimer /secured/assets/documents/en/application-note/AN4848.pdf English documents 1207848 None 645036621402383989 2023-06-18 Y /webapp/Download?colCode=AN4848 AN4848, Simple Program to Confirm PCIe Connectivity - Application Notes /secured/assets/documents/en/application-note/AN4848.pdf documents 645036621402383989 Application Note N en Extended pdf 0 Y N AN4848, Simple Program to Confirm PCIe Connectivity - Application Notes 1.2 MB AN4848 N 1390372586014711432307 /docs/en/application-note/AN4531.pdf 2016-10-31 1363012931515701443659 PSP 15 Dec 16, 2013 Application Note This document describes the requirements and step-by-step procedures for forcing the DRAM into self-refresh mode. None /docs/en/application-note/AN4531.pdf English documents 269380 None 645036621402383989 2022-12-07 N /docs/en/application-note/AN4531.pdf AN4531, Achieving Persistent DRAM on PowerQUICC III and QorIQ Processors - Application Notes /docs/en/application-note/AN4531.pdf documents 645036621402383989 Application Note N en None pdf 2 N N AN4531, Achieving Persistent DRAM on PowerQUICC III and QorIQ Processors - Application Notes 269.4 KB AN4531 N 1363012931515701443659 /secured/assets/documents/en/application-note/AN3940.pdf 2016-10-31 1264793052715706871063 PSP 16 Nov 25, 2013 Application Note AN3940: This document provides general hardware and layout considerations and guidelines for hardware engineers implementing a DDR3 memory subsystem. Registration without Disclaimer /secured/assets/documents/en/application-note/AN3940.pdf English documents 547662 None 645036621402383989 2023-06-18 Y /webapp/Download?colCode=AN3940 AN3940, Hardware and Layout Design Considerations for DDR3 SDRAM Memory Interfaces - App Note /secured/assets/documents/en/application-note/AN3940.pdf documents 645036621402383989 Application Note N en Extended Y pdf 6 Y N AN3940, Hardware and Layout Design Considerations for DDR3 SDRAM Memory Interfaces - App Note 547.7 KB AN3940 N 1264793052715706871063 /docs/en/application-note/AN4375.pdf 2016-10-31 1329517560294722281831 PSP 17 Jun 21, 2012 Application Note This document describes how to calculate the maximum frequency and transfer formats and includes eSPI programming examples. None /docs/en/application-note/AN4375.pdf English documents 216552 None 645036621402383989 2022-12-07 N /docs/en/application-note/AN4375.pdf QorIQ eSPI Controller Register Setting Considerations and Programming Examples /docs/en/application-note/AN4375.pdf documents 645036621402383989 Application Note N en None pdf 1 N N QorIQ eSPI Controller Register Setting Considerations and Programming Examples 216.6 KB AN4375 N 1329517560294722281831 /docs/en/application-note/AN3659.pdf 2016-10-31 1229718093838710459075 PSP 18 Jun 15, 2012 Application Note This document describes on-chip ROM booting from an SD card/MMC or from an EEPROM under a Linux&#13;&#10;operating system. None /docs/en/application-note/AN3659.pdf English documents 334243 None 645036621402383989 2022-12-07 N /docs/en/application-note/AN3659.pdf Booting from On-Chip ROM (eSDHC or eSPI) /docs/en/application-note/AN3659.pdf documents 645036621402383989 Application Note N en None pdf 2 N N Booting from On-Chip ROM (eSDHC or eSPI) 334.2 KB AN3659 N 1229718093838710459075 /docs/en/application-note/AN4326.pdf 2016-10-31 1309961595210675753552 PSP 19 Jul 6, 2011 Application Note This application note describes a procedure that allows users to validate the implementation of 1588-specific hardware in their system. None /docs/en/application-note/AN4326.pdf English documents 743199 None 645036621402383989 2022-12-07 /docs/en/application-note/AN4326.pdf Verification of the IEEE 1588 Interface /docs/en/application-note/AN4326.pdf documents 645036621402383989 Application Note N en None pdf 0 N Verification of the IEEE 1588 Interface 743.2 KB AN4326 N 1309961595210675753552 /secured/assets/documents/en/application-note/AN4311.pdf 2016-10-31 1305312143395731535528 PSP 20 May 13, 2011 Application Note This application note describes some reference connection schemes when interfacing the third-party clock driver chip&#8217;s output with the SerDes Reference Clock inputs of PowerQUICC<sup>&#174;</sup> or QorIQ<sup>&#174;</sup> devices. It also summarizes some recommendations for PCI Express and SRIO HSSI measurement. Registration without Disclaimer /secured/assets/documents/en/application-note/AN4311.pdf English documents 577164 None 645036621402383989 2023-06-18 Y /webapp/Download?colCode=AN4311 SerDes Reference Clock Interfacing and HSSI Measurements Recommendations /secured/assets/documents/en/application-note/AN4311.pdf documents 645036621402383989 Application Note N en Extended Y pdf Rev. 0 Y N SerDes Reference Clock Interfacing and HSSI Measurements Recommendations 577.2 KB AN4311 N 1305312143395731535528 /docs/en/application-note/AN3423.pdf 2016-10-31 1287581868481730872047 PSP 21 Oct 6, 2010 Application Note None /docs/en/application-note/AN3423.pdf English documents 141965 None 645036621402383989 2022-12-07 /docs/en/application-note/AN3423.pdf Support for IEEE 1588™ Protocol in PowerQUICC and QorIQ Processors /docs/en/application-note/AN3423.pdf documents 645036621402383989 Application Note N en None pdf 0 N Support for IEEE 1588™ Protocol in PowerQUICC and QorIQ Processors 142.0 KB AN3423 N 1287581868481730872047 /secured/assets/documents/en/application-note/AN3939.pdf 2016-10-31 1251150824863717930878 PSP 22 Jun 30, 2010 Application Note This application note describes how to use and benefit from DDR memory interleaving. Registration without Disclaimer /secured/assets/documents/en/application-note/AN3939.pdf English documents 717276 None 645036621402383989 2022-12-07 Y /webapp/Download?colCode=AN3939 DDR Interleaving for PowerQUICC and QorIQ Processors /secured/assets/documents/en/application-note/AN3939.pdf documents 645036621402383989 Application Note N en Extended Y pdf 1 Y N DDR Interleaving for PowerQUICC and QorIQ Processors 717.3 KB AN3939 N 1251150824863717930878 /docs/en/application-note/AN4064.pdf 2016-10-31 1269842191514722596708 PSP 23 Mar 28, 2010 Application Note AN4064: This document explains how to enable and utilize 36-bit physical addressing. It describes the 36-bit capabilities of the e600 and e500v2, and later processor families. Addressing and memory management in a computer system is a difficult topic that is largely beyond the scope of this document. This section explains some of the basic concepts that are essential to understand in order to develop system-level software that utilizes 36-bit physical addressing. None /docs/en/application-note/AN4064.pdf English documents 576818 None 645036621402383989 2022-12-07 /docs/en/application-note/AN4064.pdf AN4064, Utilizing 36-Bit Physical Addressing in U-Boot and Linux - Application Notes /docs/en/application-note/AN4064.pdf documents 645036621402383989 Application Note N en None pdf 0 N AN4064, Utilizing 36-Bit Physical Addressing in U-Boot and Linux - Application Notes 576.8 KB AN4064 N 1269842191514722596708 /docs/en/application-note/AN4056.pdf 2016-10-31 1264143083962735811350 PSP 24 Feb 18, 2010 Application Note This application note describes basic jitter terminology and the aspects pertaining to the SYSCLK clock design requirements. None /docs/en/application-note/AN4056.pdf English documents 514364 None 645036621402383989 2022-12-07 /docs/en/application-note/AN4056.pdf Understanding SYSCLK Jitter /docs/en/application-note/AN4056.pdf documents 645036621402383989 Application Note N en None pdf 1 N Understanding SYSCLK Jitter 514.4 KB AN4056 N 1264143083962735811350 /docs/en/application-note/AN3638.pdf 2016-10-31 1213738938672737755656 PSP 25 Oct 26, 2009 Application Note NXP Semiconductors Power Architecture&#8482;&#13;&#10;technology-based evaluation and development platforms may optionally implement a &#8220;System ID&#8221; non-volatile memory device. This device stores important configuration data about the board. None /docs/en/application-note/AN3638.pdf English documents 495318 None 645036621402383989 2022-12-07 N /docs/en/application-note/AN3638.pdf The SystemID Format for Power Architecture™ Development Systems /docs/en/application-note/AN3638.pdf documents 645036621402383989 Application Note N en None pdf 2 N N The SystemID Format for Power Architecture™ Development Systems 495.3 KB AN3638 N 1213738938672737755656 /secured/assets/documents/en/application-note/AN3646.pdf 2016-10-31 1256145464773713684480 PSP 26 Oct 21, 2009 Application Note This document is an overview of how to configure&#13;&#10;PowerQUICC<sup>&#174;</sup> III and QorIQ<sup>&#174;</sup> P1xx/P2xx devices to boot from serial RapidIO&#8482; or PCI Express&#8482; with no additional boot flash/EEPROM. Registration without Disclaimer /secured/assets/documents/en/application-note/AN3646.pdf English documents 543108 None 645036621402383989 2022-12-07 Y /webapp/Download?colCode=AN3646 Booting from Serial RapidIO™/PCI Express™ on PowerQUICC™ III and QorIQ™ P1xx/P2xx /secured/assets/documents/en/application-note/AN3646.pdf documents 645036621402383989 Application Note N en Extended pdf 0 Y N Booting from Serial RapidIO™/PCI Express™ on PowerQUICC™ III and QorIQ™ P1xx/P2xx 543.1 KB AN3646 N 1256145464773713684480 /docs/en/application-note/AN2490.pdf 2016-10-31 1060017730134725666689 PSP 27 Sep 23, 2009 Application Note Application Note None /docs/en/application-note/AN2490.pdf English documents 612895 None 645036621402383989 2022-12-07 /docs/en/application-note/AN2490.pdf MPC603e and e500 Register Model Comparison /docs/en/application-note/AN2490.pdf documents 645036621402383989 Application Note N en None pdf 1 N MPC603e and e500 Register Model Comparison 612.9 KB AN2490 N 1060017730134725666689 /secured/assets/documents/en/application-note/AN3869.pdf 2016-10-31 1244236817778728476903 PSP 28 Jun 5, 2009 Application Note This application note explains configuration&#13;&#10;requirements to assist users to successfully program and set up this interface type. It also compares SGMII to other gigabit Ethernet standards and interfaces. Registration without Disclaimer /secured/assets/documents/en/application-note/AN3869.pdf English documents 692438 None 645036621402383989 2022-12-07 Y /webapp/Download?colCode=AN3869 Implementing SGMII Interfaces on the PowerQUICC™ III /secured/assets/documents/en/application-note/AN3869.pdf documents 645036621402383989 Application Note N en Extended pdf 0 Y N Implementing SGMII Interfaces on the PowerQUICC™ III 692.4 KB AN3869 N 1244236817778728476903 /secured/assets/documents/en/application-note/AN2919.pdf 2016-10-31 1119553728324723212395 PSP 29 Dec 31, 2008 Application Note This document explains how the frequency divider to calculate the SCL speed of the I2C interface is determined for the MPC824x, MPC83xx, MPC85xx, and MPC86xx devices. Registration without Disclaimer /secured/assets/documents/en/application-note/AN2919.pdf English documents 611358 None 645036621402383989 2022-12-07 Y /webapp/Download?colCode=AN2919 Determining the I2C Frequency Divider Ratio for SCL /secured/assets/documents/en/application-note/AN2919.pdf documents 645036621402383989 Application Note N en Extended pdf 5 Y N Determining the I2C Frequency Divider Ratio for SCL 611.4 KB AN2919 N 1119553728324723212395 /docs/en/application-note/AN3542.pdf 2016-10-31 1202329207598722883383 PSP 30 Jan 25, 2008 Application Note AN3542: This application note discusses the differences between SMP and AMP (asymmetric multi-processor) OSs, booting options and features of the MPC8572E, and configuration of shared and non-shared resources between cores. This application note also provides a description of the boot process implemented by Uboot and Linux that is provided as part of the MPC8572E development system board support package. None /docs/en/application-note/AN3542.pdf English documents 519909 None 645036621402383989 2022-12-07 /docs/en/application-note/AN3542.pdf AN3542, SMP Boot Process for Dual E500 Cores - Application Notes /docs/en/application-note/AN3542.pdf documents 645036621402383989 Application Note N en None pdf 0 N AN3542, SMP Boot Process for Dual E500 Cores - Application Notes 519.9 KB AN3542 N 1202329207598722883383 /docs/en/application-note/AN3544.pdf 2016-10-31 1198270786976715604383 PSP 31 Dec 21, 2007 Application Note This application note provides an overview and specific strategies for cache coherency and potential performance impacts in the PowerQUICC<sup>&#174;</sup> II Pro and PowerQUICC III families. It focuses on data coherency and potential system issues, as well as some concerns associated with having multiple DMA devices. It also discusses the specific steps and interdependencies required to implement hardware enforced cache coherency. None /docs/en/application-note/AN3544.pdf English documents 547694 None 645036621402383989 2022-12-07 /docs/en/application-note/AN3544.pdf PowerQUICC™ Data Cache Coherency /docs/en/application-note/AN3544.pdf documents 645036621402383989 Application Note N en None pdf 0 N PowerQUICC™ Data Cache Coherency 547.7 KB AN3544 N 1198270786976715604383 /docs/en/application-note/AN3441.pdf 2016-10-31 1191253168152709402147 PSP 32 Dec 17, 2007 Application Note This document describes aspects of memory synchronization and cache coherency requirements for NXP&#8217;s PowerQUICC<sup>&#174;</sup>&#8482; III product family. Coherency and synchronization need be considered, both for data and instructions, when initializing memory or moving memory contents from one location to another. None /docs/en/application-note/AN3441.pdf English documents 188954 None 645036621402383989 2022-12-07 /docs/en/application-note/AN3441.pdf Coherency and Synchronization Requirements for PowerQUICC™ III /docs/en/application-note/AN3441.pdf documents 645036621402383989 Application Note N en None pdf 1 N Coherency and Synchronization Requirements for PowerQUICC™ III 189.0 KB AN3441 N 1191253168152709402147 /docs/en/application-note/AN3537.pdf 2016-10-31 1196114880779719950774 PSP 33 Dec 6, 2007 Application Note The enhanced three-speed Ethernet controller (eTSEC) offered on many PowerQUICC&#8482; II Pro, PowerQUICC&#8482; III, and other devices, allows for flexible manipulation of incoming and outgoing Ethernet data. One such feature is the ability to receive and propagate padded, or &#8220;shimmed,&#8221; OSI layer 2 data to accommodate custom routing or direction of Ethernet data within a network. This application note describes what the shimming functionality does and the details of how to best utilize it. None /docs/en/application-note/AN3537.pdf English documents 497175 None 645036621402383989 2022-12-07 /docs/en/application-note/AN3537.pdf Accommodating Layer 2 Padding (Shimming) with the Enhanced Three-Speed Ethernet Controller (eTSEC) /docs/en/application-note/AN3537.pdf documents 645036621402383989 Application Note N en None pdf 1 N Accommodating Layer 2 Padding (Shimming) with the Enhanced Three-Speed Ethernet Controller (eTSEC) 497.2 KB AN3537 N 1196114880779719950774 /docs/en/application-note/AN3532.pdf 2016-10-31 1196228463425717224884 PSP 34 Nov 27, 2007 Application Note This application note provides an introduction to the error correcting code (ECC) technology as well as an aid to initialization and error recovery on Our PowerQUICC<sup>&#174;</sup> III family of processors. None /docs/en/application-note/AN3532.pdf English documents 572952 None 645036621402383989 2022-12-07 /docs/en/application-note/AN3532.pdf Error Correction and Error Handling on PowerQUICC (TM) III Processors /docs/en/application-note/AN3532.pdf documents 645036621402383989 Application Note N en None pdf 0 N Error Correction and Error Handling on PowerQUICC (TM) III Processors 573.0 KB AN3532 N 1196228463425717224884 /docs/en/application-note/AN3445.pdf 2016-10-31 1194389310604697206738 PSP 35 Oct 31, 2007 Application Note AN3445: This application note outlines general, high-level, architectural differences between the e300 and e500 family processors. The e300 family (which are based on the original 603 design) was designed to the original PowerPC architecture definition. The e500v1 and e500v2 processors are designed to what was originally the PowerPC Book E architecture and NXP?s embedded implementation standards (EIS). None /docs/en/application-note/AN3445.pdf English documents 934951 None 645036621402383989 2022-12-07 /docs/en/application-note/AN3445.pdf AN3445, Migrating from e300- to e500-Based Integrated Devices - Application Notes /docs/en/application-note/AN3445.pdf documents 645036621402383989 Application Note N en None pdf 0 N AN3445, Migrating from e300- to e500-Based Integrated Devices - Application Notes 935.0 KB AN3445 N 1194389310604697206738 /docs/en/application-note/AN3531.pdf 2016-10-31 1194389312415718217914 PSP 36 Oct 31, 2007 Application Note AN3531: This application note outlines general, high-level, architectural differences between the e600 and e500 family processors. Is intended as a general guideline for programmers and system designers who are assessing the efforts required in migrating to e500-based devices. None /docs/en/application-note/AN3531.pdf English documents 961596 None 645036621402383989 2022-12-07 N /docs/en/application-note/AN3531.pdf AN3531, Migrating from e600- to e500-Based Integrated Devices - Application Notes /docs/en/application-note/AN3531.pdf documents 645036621402383989 Application Note N en None pdf 0 N N AN3531, Migrating from e600- to e500-Based Integrated Devices - Application Notes 961.6 KB AN3531 N 1194389312415718217914 /docs/en/application-note/AN2910.pdf 2016-10-31 1128961595061725581551 PSP 37 Mar 27, 2007 Application Note These design guidelines are applicable for products that leverage the DDR2 SDRAM IP core, and are based on a compilation of internal platforms designed by NXP Semiconductors, Inc. These guidelines are constructed in such a fashion as to minimize board-related issues across multiple memory topologies while allowing maximum flexibility for the board designer. None /docs/en/application-note/AN2910.pdf English documents 619650 None 645036621402383989 2022-12-07 /docs/en/application-note/AN2910.pdf Hardware and Layout Design Considerations for DDR2 SDRAM Memory Interfaces /docs/en/application-note/AN2910.pdf documents 645036621402383989 Application Note N en None pdf 2 N Hardware and Layout Design Considerations for DDR2 SDRAM Memory Interfaces 619.7 KB AN2910 N 1128961595061725581551 /docs/en/application-note/AN2665.pdf 2016-10-31 1112972998032717039588 PSP 38 Apr 8, 2005 Application Note AN2665: This application note provides information to programmers so that they may write optimal code for the PowerPC ? e500 embedded microprocessor cores. The e500 core implements the Book E version of the PowerPC architecture. In addition, the e500 core adheres to the NXP Book E implementation standards (EIS). These standards were developed to ensure consistency among NXP?s Book E implementations. None /docs/en/application-note/AN2665.pdf English documents 799625 None 645036621402383989 2022-12-07 /docs/en/application-note/AN2665.pdf AN2665, e500 Software Optimization Guide (eSOG) - Application Notes /docs/en/application-note/AN2665.pdf documents 645036621402383989 Application Note N en None pdf 0 N AN2665, e500 Software Optimization Guide (eSOG) - Application Notes 799.6 KB AN2665 N 1112972998032717039588 Application Note Software 1 /docs/en/application-note-software/AN3372.pdf 2016-10-31 1181767584945705509512 PSP 40 Jun 13, 2007 Application Note Software This application note addresses a common challenge encountered during circuit board testing with some of the newer NXP microprocessors. It is common practice for board testing houses to test for shorts on the power rails by measuring the resistance from a power rail to the ground rail. In older technologies, this is a reasonable approach. However, this application note explains why this approach can be problematic when used with devices in newer technologies. None /docs/en/application-note-software/AN3372.pdf English documents 163681 None 789425793691620447 2022-12-07 /docs/en/application-note-software/AN3372.pdf Challenges in Testing for Power Rail Shorts with New Technologies /docs/en/application-note-software/AN3372.pdf documents 789425793691620447 Application Note Software N en None pdf 0 N Challenges in Testing for Power Rail Shorts with New Technologies 163.7 KB AN3372 N 1181767584945705509512 Brochure 1 /docs/en/brochure/P2_Family_App_Bro.pdf 2016-10-31 1244825988989716147424 PSP 41 Jun 12, 2009 Brochure QorIQ<sup>&#174;</sup> communications processors are the next-generation evolution of our leading PowerQUICC<sup>&#174;</sup> &#174; communications processors. Based on high-performance e500 cores built on Power Architecture &#174; technology. The QorIQ P2 platform series, which includes the P2020 and P2010 communications processors, delivers unprecedented performance per watt. The series delivers dual- and single-core frequencies from 800 MHz to 1.2 GHz. None /docs/en/brochure/P2_Family_App_Bro.pdf English documents 4070334 None 712453003803778552 2022-12-07 /docs/en/brochure/P2_Family_App_Bro.pdf QorIQ P2 Family Communications Processors - Application Brief /docs/en/brochure/P2_Family_App_Bro.pdf documents 712453003803778552 Brochure N en None pdf 0 N QorIQ P2 Family Communications Processors - Application Brief 4.1 MB P2_FAMILY_APP_BRO N 1244825988989716147424 Data Sheet 2 /secured/assets/documents/en/data-sheet/P2010EC.pdf 2016-10-31 1302304654412717382496 PSP 3 Mar 14, 2016 Data Sheet This document describes the electrical characteristics of the P2010. Registration without Disclaimer /secured/assets/documents/en/data-sheet/P2010EC.pdf English documents 2074938 None 980000996212993340 2023-06-18 Y /webapp/Download?colCode=P2010EC P2010 QorIQ Integrated Processor Hardware Specifications - Data Sheets /secured/assets/documents/en/data-sheet/P2010EC.pdf documents 980000996212993340 Data Sheet N en Extended pdf 3 Y N P2010 QorIQ Integrated Processor Hardware Specifications - Data Sheets 2.1 MB P2010EC N 1302304654412717382496 /secured/assets/documents/en/data-sheet/P2020EC.pdf 2016-10-31 1302304608307727528114 PSP 4 Mar 14, 2016 Data Sheet This document describes the P2020 electrical characteristics. Registration without Disclaimer /secured/assets/documents/en/data-sheet/P2020EC.pdf English documents 1899579 None 980000996212993340 2023-06-18 Y /webapp/Download?colCode=P2020EC P2020 QorIQ Integrated Processor Hardware Specifications - Data Sheets /secured/assets/documents/en/data-sheet/P2020EC.pdf documents 980000996212993340 Data Sheet N en Extended pdf 3 Y N P2020 QorIQ Integrated Processor Hardware Specifications - Data Sheets 1.9 MB P2020EC N 1302304608307727528114 Fact Sheet 5 /docs/en/fact-sheet/P2020UTMAPPFS.pdf 2016-10-31 1267326981318733118436 PSP 43 Feb 14, 2020 Fact Sheet NXP&#8217;s UTM and security appliance solution exemplifies our solutions-centric approach by bringing together all three elements needed for the development of a complete UTM security appliance: processors, software and an ecosystem of hardware and software partners, providing our customers a complete solution to deliver differentiated products to market. None /docs/en/fact-sheet/P2020UTMAPPFS.pdf English documents 969061 None 736675474163315314 2022-12-07 N /docs/en/fact-sheet/P2020UTMAPPFS.pdf QorIQ™ P2020 UTM/Security Appliance Solution /docs/en/fact-sheet/P2020UTMAPPFS.pdf documents 736675474163315314 Fact Sheet N en None Y pdf 1 N N QorIQ™ P2020 UTM/Security Appliance Solution 969.1 KB P2020UTMAPPFS N 1267326981318733118436 /docs/en/fact-sheet/LTEWIMAXFS.pdf 2016-10-31 1192384455671724743414 PSP 44 Feb 19, 2010 Fact Sheet None /docs/en/fact-sheet/LTEWIMAXFS.pdf English documents 441802 None 736675474163315314 2022-12-07 /docs/en/fact-sheet/LTEWIMAXFS.pdf Modular AdvancedMC Platform for Broadband/LTE Base Stations Fact Sheet /docs/en/fact-sheet/LTEWIMAXFS.pdf documents 736675474163315314 Fact Sheet N en None pdf 2 N Modular AdvancedMC Platform for Broadband/LTE Base Stations Fact Sheet 441.8 KB LTEWIMAXFS N 1192384455671724743414 /docs/en/fact-sheet/P2020DS.pdf 2016-10-31 1244223699499702220156 PSP 45 Jun 5, 2009 Fact Sheet None /docs/en/fact-sheet/P2020DS.pdf English documents 304717 None 736675474163315314 2022-12-07 /docs/en/fact-sheet/P2020DS.pdf P2020 Development System /docs/en/fact-sheet/P2020DS.pdf documents 736675474163315314 Fact Sheet N en None pdf v4 N P2020 Development System 304.7 KB P2020DS N 1244223699499702220156 /docs/en/fact-sheet/P2020RDB.pdf 2016-10-31 1244223699965708466197 PSP 46 Jun 5, 2009 Fact Sheet None /docs/en/fact-sheet/P2020RDB.pdf English documents 447187 None 736675474163315314 2022-12-07 /docs/en/fact-sheet/P2020RDB.pdf P2020 Reference Design Board /docs/en/fact-sheet/P2020RDB.pdf documents 736675474163315314 Fact Sheet N en None pdf v4 N P2020 Reference Design Board 447.2 KB P2020RDB N 1244223699965708466197 /docs/en/fact-sheet/QP20XXFS.pdf 2016-10-31 1228778885836687636815 PSP 1 Feb 14, 2020 Fact Sheet Fact Sheet The QorIQ<sup>&#174;</sup> P2 platform series, which includes the P2020 and P2010 communications processors, delivers unprecedented performance per watt for a wide variety of applications in the networking, telecom, military and industrial markets. The series delivers dual- and single-core frequencies up to 1.2 GHz on a 45nm technology low-power platform. None /docs/en/fact-sheet/QP20XXFS.pdf English 229476 None Fact Sheet 2022-12-07 N /docs/en/fact-sheet/QP20XXFS.pdf Fact Sheet /docs/en/fact-sheet/QP20XXFS.pdf documents 736675474163315314 Fact Sheet N Y en None Y t523 pdf 5 N N Fact Sheet 229.5 KB QP20XXFS N 1228778885836687636815 Product Brief 1 /secured/assets/documents/en/product-brief/P2020PB.pdf 2016-10-31 1232486626815740001812 PSP 47 Jun 22, 2012 Product Brief This document provides an overview of features and functionality of the P2020 and P2010 QorIQ<sup>&#174;</sup> communications processors. Registration without Disclaimer /secured/assets/documents/en/product-brief/P2020PB.pdf English documents 206013 None 899114358132306053 2022-12-07 Y /webapp/Download?colCode=P2020PB P2020/P2010 QorIQ Communications Processor Product Brief /secured/assets/documents/en/product-brief/P2020PB.pdf documents 899114358132306053 Product Brief N en Extended pdf 1 Y N P2020/P2010 QorIQ Communications Processor Product Brief 206.0 KB P2020PB N 1232486626815740001812 Reference Manual 5 /secured/assets/documents/en/reference-manual/EREF_RM.pdf 2016-10-31 1319210247754725815434 PSP 5 Jun 26, 2014 Reference Manual This reference manual describes the resources defined for the Power ISA embedded environment. Registration without Disclaimer /secured/assets/documents/en/reference-manual/EREF_RM.pdf English documents 10448185 None 500633505221135046 2022-12-07 Y /webapp/Download?colCode=EREF_RM EREF_RM, EREF: A Programmer's Reference Manual for Freescale Power Architecture Processors - Reference Manual /secured/assets/documents/en/reference-manual/EREF_RM.pdf documents 500633505221135046 Reference Manual N en Extended Y pdf 1 Y N EREF_RM, EREF: A Programmer's Reference Manual for Freescale Power Architecture Processors - Reference Manual 10.4 MB EREF_RM N 1319210247754725815434 /secured/assets/documents/en/reference-manual/P2020SEC.pdf 2012-12-19 1355978300497711919636 PSP 6 Dec 19, 2012 Reference Manual This document describes the functionality of NXP&#8217;s integrated security engine (SEC 3.1). The SEC 3.1 is designed to off-load computationally intensive security functions, such as key generation and exchange, authentication, and bulk encryption from the processor core of the SoC. Registration without Disclaimer /secured/assets/documents/en/reference-manual/P2020SEC.pdf English documents 1218749 None 500633505221135046 2023-06-18 Y /webapp/Download?colCode=P2020SECRM P2020 Security (SEC 3.1) Reference Manual /secured/assets/documents/en/reference-manual/P2020SEC.pdf documents 500633505221135046 Reference Manual N en Extended Y pdf 0 Y N P2020 Security (SEC 3.1) Reference Manual 1.2 MB P2020SECRM N 1355978300497711919636 /secured/assets/documents/en/reference-manual/EMBMCRM.pdf 2016-10-31 1247173677125723218813 PSP 7 Jul 20, 2009 Reference Manual Multicore devices provide a path forward for increased performance. This path requires comprehensive and pervasive system and software changes as well as new, innovative hardware designs to ensure that the software can take advantage of the increased computational power. NXP Semiconductors, Inc. has years of experience with many types of embedded multicore devices and thus can ensure that all necessary components are present to ease the software burden and to avoid having an inefficient core. This bala Registration without Disclaimer /secured/assets/documents/en/reference-manual/EMBMCRM.pdf English documents 1486324 None 500633505221135046 2022-12-07 Y /webapp/Download?colCode=EMBMCRM Embedded Multicore: An Introduction /secured/assets/documents/en/reference-manual/EMBMCRM.pdf documents 500633505221135046 Reference Manual N en Extended Y pdf 0 Y N Embedded Multicore: An Introduction 1.5 MB EMBMCRM N 1247173677125723218813 /docs/en/reference-manual/E500CORERM.pdf 2016-10-31 111qmdXB PSP 8 May 11, 2005 Reference Manual The primary objective of this user&#8217;s manual is to describe the functionality of the e500 embedded microprocessor core for software and hardware developers. The e500 processor core is a low-power implementation of the family of reduced instruction set computing (RISC) embedded processors that implement the Book E definition of the PowerPC architecture. The e500 is a 32-bit implementation of the Book E architecture using the lower words in the 64-bit general-purpose registers (GPRs). None /docs/en/reference-manual/E500CORERM.pdf English documents 5707515 None 500633505221135046 2022-12-07 /docs/en/reference-manual/E500CORERM.pdf PowerPC ™ e500 Core Family - Reference Manual /docs/en/reference-manual/E500CORERM.pdf documents 500633505221135046 Reference Manual N en None pdf 1 N PowerPC ™ e500 Core Family - Reference Manual 5.7 MB E500CORERM N 111qmdXB /secured/assets/documents/en/reference-manual/P2020RM.pdf 2016-10-31 1249275244228708113744 PSP 2 Dec 18, 2012 Reference Manual Reference Manual This reference manual defines the functionality of the P2020. The chip combines dual Power ArchitectureR e500v2 processor cores with system logic required for networking, wireless infrastructure, and telecommunications applications.&#13;&#10; Registration without Disclaimer /secured/assets/documents/en/reference-manual/P2020RM.pdf English 24199412 None Reference Manual 2022-12-07 Y /webapp/Download?colCode=P2020RM P2020 QorIQ Integrated Processor Reference Manual /secured/assets/documents/en/reference-manual/P2020RM.pdf documents 500633505221135046 Reference Manual N Y en Extended t877 pdf 2 Y N P2020 QorIQ Integrated Processor Reference Manual 24.2 MB P2020RM N 1249275244228708113744 Supporting Information 2 /docs/en/supporting-information/FSLNISTCAVP.pdf 2016-11-09 1368836090577704535160 PSP 48 Oct 28, 2016 Supporting Information FSLNISTCAVP: NXP<sup>&#174;</sup> Semiconductors has performed NIST CAVP testing of cryptographic accelerators (called Execution Units or EUs) found in multiple product families, including the PowerQUICC<sup>&#174;</sup> and QorIQ<sup>&#174;</sup> embedded communications processors, and the StarCore<sup>&#174;</sup> digital signal processors. None /docs/en/supporting-information/FSLNISTCAVP.pdf English documents 303546 None 371282830530968666 2022-12-07 N /docs/en/supporting-information/FSLNISTCAVP.pdf FSLNISTCAVP, NIST Crypto Algorithm Validation Program Certifications for NXP<sup>®</sup> Cryptographic Accelerators - White Paper /docs/en/supporting-information/FSLNISTCAVP.pdf documents 371282830530968666 Supporting Information N en None Y pdf 1.9 N N FSLNISTCAVP, NIST Crypto Algorithm Validation Program Certifications for NXP<sup>®</sup> Cryptographic Accelerators - White Paper 303.5 KB FSLNISTCAVP N 1368836090577704535160 /docs/en/supporting-information/P2020FAMPECI.pdf 2016-10-31 1232680174357742940244 PSP 49 Dec 10, 2010 Supporting Information Customer Export Control Information Document None /docs/en/supporting-information/P2020FAMPECI.pdf English documents 158367 None 371282830530968666 2023-06-19 N /docs/en/supporting-information/P2020FAMPECI.pdf P2020 Family Customer Export Control Information /docs/en/supporting-information/P2020FAMPECI.pdf documents 371282830530968666 Supporting Information N en None Y pdf 2 N N P2020 Family Customer Export Control Information 158.4 KB P2020FAMPECI N 1232680174357742940244 Technical Notes 1 /secured/assets/documents/en/engineering-bulletin/EB739.pdf 2016-10-31 1299186935006725024525 PSP 42 Mar 3, 2011 Technical Notes Provides a COMe pin-out for QorIQ<sup>&#174;</sup> devices Registration without Disclaimer /secured/assets/documents/en/engineering-bulletin/EB739.pdf English documents 492591 None 389245547230346745 2022-12-07 Y /webapp/Download?colCode=EB739 COM Express Pin Assignments for QorIQ Devices /secured/assets/documents/en/engineering-bulletin/EB739.pdf documents 389245547230346745 Technical Notes N en Extended pdf 0 Y N COM Express Pin Assignments for QorIQ Devices 492.6 KB EB739 N 1299186935006725024525 User Guide 1 /docs/en/user-guide/SPECTRE-MELTDOWN-POWER-ISA-DOC 2019-12-18 https://docs.nxp.com/bundle/GUID-805CC0EA-4001-47AD-86CD-4F340751F6B7/page/GUID-17B5D04F-6471-4EC6-BEB9-DE4D0AFA034A.html /bundle/GUID-805CC0EA-4001-47AD-86CD-4F340751F6B7/page/GUID-17B5D04F-6471-4EC6-BEB9-DE4D0AFA034A.html Y Y 1576719019599707128294 PSP 39 Nov 14, 2019 User Guide None /docs/en/user-guide/SPECTRE-MELTDOWN-POWER-ISA-DOC English Y documents Y None 132339537837198660 2022-12-07 N https://docs.nxp.com/bundle/GUID-805CC0EA-4001-47AD-86CD-4F340751F6B7/page/GUID-17B5D04F-6471-4EC6-BEB9-DE4D0AFA034A.html Spectre and Meltdown Updates for Power ISA Cores /docs/en/user-guide/SPECTRE-MELTDOWN-POWER-ISA-DOC documents 132339537837198660 User Guide N en None Y 1 N N Spectre and Meltdown Updates for Power ISA Cores SPECTRE-MELTDOWN-POWER-ISA-DOC N 1576719019599707128294 White Paper 3 /docs/en/white-paper/SPECTREPPCWP.pdf 2020-01-30 1580452712610724357770 PSP 50 Jan 30, 2020 White Paper In this paper, we present the mitigations for Spectre variant 1 and Spectre variant 2 for NXP PowerPC processors. The NXP PowerPC processors are not vulnerable to the Meltdown attack, Spectre variant 1.1/1.2, or Spectre variant 4. None /docs/en/white-paper/SPECTREPPCWP.pdf English documents 317053 None 918633085541740938 2022-12-07 N /docs/en/white-paper/SPECTREPPCWP.pdf Speculative Execution Vulnerabilities and Mitigations on NXP PowerPC Processors White Paper /docs/en/white-paper/SPECTREPPCWP.pdf documents 918633085541740938 White Paper N en None Y pdf 0 N N Speculative Execution Vulnerabilities and Mitigations on NXP PowerPC Processors White Paper 317.1 KB SPECTREPPCWP N 1580452712610724357770 /docs/en/white-paper/LTEWHTPPRCRTBLA4.pdf 2016-10-31 1289917463417712987902 PSP 51 Nov 16, 2010 White Paper CritialBlue&#13;&#10;&#13;&#10;Prism software None /docs/en/white-paper/LTEWHTPPRCRTBLA4.pdf English documents 673125 None 918633085541740938 2022-12-07 /docs/en/white-paper/LTEWHTPPRCRTBLA4.pdf Tuning QorIQ Processor Performance /docs/en/white-paper/LTEWHTPPRCRTBLA4.pdf documents 918633085541740938 White Paper N en None pdf 0 N Tuning QorIQ Processor Performance 673.1 KB LTEWHTPPRCRTBLA4 N 1289917463417712987902 /secured/assets/documents/en/white-paper/CRYPTOWP.pdf 2016-10-31 1227561595497709456436 PSP 52 Aug 15, 2008 White Paper Network security protocols and applications use a variety of cryptographic algorithms to achieve these high-level goals. Because cryptography is computationally intensive, hardware acceleration is highly desirable when cryptographic algorithms are frequent system functions. Registration without Disclaimer /secured/assets/documents/en/white-paper/CRYPTOWP.pdf English documents 580121 None 918633085541740938 2022-12-07 Y /webapp/Download?colCode=CRYPTOWP Understanding Cryptographic Performance /secured/assets/documents/en/white-paper/CRYPTOWP.pdf documents 918633085541740938 White Paper N en Extended Y pdf 3 Y N Understanding Cryptographic Performance 580.1 KB CRYPTOWP N 1227561595497709456436 true Y Products

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