S32R47 High-Performance Imaging Radar Processor for Automotive and Industrial Applications

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  • This page contains information on a preproduction product. Specifications and information herein are subject to change without notice. For additional information contact support or your sales representative.

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The S32R47 is a radar application microprocessor unit (MPU) that enables next-generation imaging radar sensors to support ADAS Level 2+ to Level 4 addressing the most demanding use cases like debris detection in inclement weather. Dedicated radar processing accelerators meet demanding sensor level features for long distance, fine resolution and extended dynamic range.

The S3243 is a package compatible variant of the S32R47 to serve different performance classes.

The chip is highly software compatible with NXP’s S32R41 and S32R45 radar processors and SAF85xx radar SoCs.

Block Diagram

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S32R47

S32R47 Block Diagram

S32R43

S32R43 Block Diagram
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Features

High-Performance Safe Compute

  • 4 x Arm® Cortex®-A53 @ 1200 MHz with Neon and FPU
  • 3 x Arm Cortex-M7 @ 400 MHz with lock-step safety core configuration and FPU

Radar Processing Acceleration

  • 2 x SPT 3.8 @ 600 MHz (16-way complex, four threads)
  • 2 x BBE32EP @ 600 MHz
  • 2 x post-processing accelerator (KQ8PPA 1 and KQ8PPA 2)

Memory

  • 8 MB SRAM
  • LPDDR4x and LPDDR5 supported

Connectivity

  • 4 x MIPI CSI2
  • 3 x SGMII Ethernet 100/1000/2500 Mbit/s, MACsec HW support
  • 1 PCIe Gen 2/3

Safety

  • ISO 26262 SEooC ASIL B(D)

Security

  • In-field updatable Hardware Security Engine (HSE) with comprehensive feature set
  • EVITA Full, SHE+, ISO/SAE 21434 compliant product development

Temperature

  • -40 ºC to 150 °C (Tj) AEC-Q100 Grade-1

Feature Comparison Between S32R47 and S32R43

Feature S32R47 S32R43
High Performance Safe Compute 4 x Arm Cortex-A53 @1200 MHz 4 x Arm Cortex-A53 @800 MHz
Post Processing Acceleration 2 x KQ8PPA 1 x KQ8PPA
Radar Processing Acceleration 2 x SPT3.8 1 x SPT3.8
Memory Capacity for Demanding Radar Applications LPDDR5 and LPDDR4x LPDDR5 and LPDDR4x
Connected and Scalable 3 2
Package 548 FCCSP I5*15 0.5
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