Application Note (14)
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Understanding SYSCLK Jitter[AN4056]
Design Files
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PowerQUICC® Processor with CPM (1 SCC, 1 SMC), 10/100 Ethernet
The MPC859DSL Integrated Communications Controller is a versatile one-chip integrated microprocessor and peripheral combination that can be used in a variety of controller applications. It particularly excels in CPE applications including DSL modems, IADs, and residential gateways. Like the MPC866, the MPC859DSL is a 0.18 micron version of the PowerQUICC® Family and can operate up to 66 MHz on the MPC8xx core. It has a 1.8 V core and a 3.3 V I/O operation.
The MPC859DSL is a Power Architecture-based derivative of NXP® Semiconductors' Quad Integrated Communications Controller (PowerQUICC). The embedded CPU on the MPC859DSL is the MPC8xx core, a 32-bit microprocessor built on Power Architecture technology, incorporating memory management units (MMUs) and instruction and data caches. The memory controller supports many memory types, including SDRAM. The CPM (Communications Processing Module) is optimized for CPE applications supporting simultaneous operation of Fast Ethernet (MII) and parallel ATM (UTOPIA), UTOPIA II Multi-PHY (up to 4 addresses), and many more features.
Product Details
Features
- Single-issue, 32-bit version of the core (compatible with Power Architecture technology) with 32, 32-bit general-purpose registers (GPRs)
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The MPC859DSL provides enhanced ATM functionality over that of the
MPC860SAR.
The MPC859DSL adds major new features available in
"enhanced SAR" (ESAR)
mode, including the following:
- Multiple APC priority levels available to support a range of traffic pace requirements
- Port-to-port switching capability without the need for RAM-based microcode
- Simultaneous MII (100Base-T) and UTOPIA (half-duplex) capability
- Parameter RAM for both SPI and I²C can be relocated without RAM-based microcode
- Supports full-duplex UTOPIA leader (ATM side) operation using a "split" bus
- Up to 32-bit data bus (dynamic bus sizing for 8, 16, and 32 bits)
- UTOPIA port supports up to 4 PHY addresses
- Complete static design
- Memory controller (eight banks)
- General-purpose timers
- Fast Ethernet controller (FEC)
- System integration unit (SIU)
- Interrupts
- Communications processor module (CPM)
- Four baud rate generators
- One SCC (serial communication controller) for Ethernet (SCC1)
- One SMC (serial management channel) for UART (SMC1)
- One SPI (serial peripheral interface)
- One I²C (inter-integrated circuit) port
- Parallel interface port (PIP)
- One PCMCIA socket (Port B)
- Low power support
- Debug interface
- 1.8 V core, 3.3 V I/O
- 357-pin PBGA package
Comparison Table
MPC866 Family Versions and Masks
| Qual | Process | Mask | IMMR [16:31] | |
|---|---|---|---|---|
| Rev 0.3 | MC | HiP6W | 3L90H | 0x0800 |
| Rev A.0 | MC | HiP6W | 0L96R | 0x0801 |
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Documentation
Quick reference to our documentation types
1-10 of 28 documents
Compact List
Design Resources
Hardware
Quick reference to our
board types.
3 hardware offerings
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Emulators, Probes, and ProgrammersCodeWarrior® TAP
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Emulators, Probes, and ProgrammersUSB TAP for PowerQUICC® I
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Evaluation and Development BoardsMPC866 Application Development System Kit
Software
Quick reference to our software types.
2 software files
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Development IDEs and Build Tools
CodeWarrior® Development Suites for Networked ApplicationsFeatured
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Software Development Resources
Professional Support for Processors and Microcontrollers
Note: For better experience, software downloads are recommended on desktop.
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Independent Design House (IDH)
Hardware/Software Engineering Services
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Independent Design House (IDH)
Signal Integrity analysis
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Android & Linux Design Services
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