S32N7 Super-Integration Processor for Software-Defined Vehicles

S32N7
Preproduction
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NXP’s S32N7 processor series breaks silos to drive cross-domain innovation through Edge AI, with a mission to deliver differentiating value at the heart of the software-defined vehicle (SDV).

S32N7 enables vehicles to become intelligent and evolve through AI and frequent over-the-air (OTA) updates. It consolidates up to eight domains within safe hardware partitions, delivering ASIL D real-time performance and robust cybersecurity.

  • Application cores unlock efficient data orchestration
  • Integrated communication engines enable low-latency access to zones, sensors and actuators
  • Built-in AI/data accelerators support predictive intelligence
  • Peripheral Component Interconnect express (PCIe) enables seamless data flow and modular expansion while compatible system on a chip (SoC) variants and a unified software enable reuse and scalable platform implementations

S32N7 empowers OEMs to drive innovation, set new benchmarks for quality and serve multiple markets. Use cases include cost-cutting predictive insights for fleet managers and enhanced user experience for drivers, both delivering unmatched efficiency, safety and personalization.

Block Diagram

S32N7

S32N7 Block Diagram
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Features

Processors

  • Up to 8x split-lock Arm® Cortex®-A78AE cores operating at up to 1.8 GHz
  • Up to 12x split-lock Arm Cortex-R52 cores operating at up to 1.4 GHz
  • Reduced instruction set computer (RISC-V)-based accelerator for networking, math and data-intensive workloads
  • eIQ® Neutron neural processing unit (NPU) for vehicle-core NeuroNetwork offload
  • Independent safety system manager
  • Independent safety communication manager
  • Independent housekeeping controller

Low-Power Modes

  • Up to 5x power modes supporting always-ON, ultra-low-power and AI-enabled low-power operation capabilities
  • Suspend-to-RAM support
  • Periodic wake support

Memory

  • Up to 2x low-power double data rate (LPDDR) 4X/5/5X DRAM interfaces
  • Up to 36 MB platform static random-access memory (SRAM)
  • 2x channel non-volatile memory (NVM) interface supporting serial, quad and octal NOR memory
  • 1x universal flash storage (UFS) 3.1 interface
  • eMMC 5.1 NAND flash and SD card/secure digital input output (SDIO) flash support

Application Integration

  • Full on-chip hardware isolation and virtualization for isolated and mixed‑criticality applications applications
  • Core-to-pin virtual hardware isolation technology supports freedom from interference

Functional Safety

  • Independent system manager handles the functional safety across all SoC partitions
  • Hardware provides freedom from interference and virtualized Quality of Service (QoS) mechanisms for shared resources
    • Keeps fault impact at the integrated-ECU level with local reactions
    • Runtime operating mode, safe-stop and reset all controlled individually for each integrated electronic control unit (ECU), reducing the number of faults that lead to SoC reset
  • Processor developed according to processes that are certified to ISO 26262 for ASIL D functional safety

Security

  • The integrated high security engine (HSE2) security engine provides advanced, future‑proof security capabilities and high performance to enable:
    • A post‑quantum hardware root‑of‑trust
    • Fast secure boot plus security services and key management
    • Secure debug and secure update
    • Real‑time, high‑speed message signing, authentication and encryption for secure communications and more
  • Public key infrastructure and side-channel attack resistance
  • Distributed security approach to provide increased availability of security services, increased parallelism of security operations, clearer prioritization between tasks and minimized latency
  • Developed according to cybersecurity processes that are certified to ISO/SAE 21434, UN R155 and also targeted for SESIP Level 2 certification
  • Up to 2x asymmetric crypto accelerators support secure communications and secure OTA updates
  • Up to 2x symmetric accelerators in-vehicle communications

Communication and Networking

  • An independent communication subsystem manages low-speed communication interfaces
  • Controller area network Hub virtualizes CAN I/O and allows applications to share CAN I/O pins, routes CAN frames to multiple CAN controllers and offloads CAN-to-CAN routing from the host core
  • Multiple controller area network flexible data-rate (CAN FD), controller area network extended length (CAN XL), local interconnect network (LIN) and FlexRay® interfaces
  • Integrated Time-Sensitive Networking (TSN) Ethernet switch supporting interfaces speeds between 10 Mbps to 10 Gbps
  • Per-port Inline encryption with media access control security (MACsec) acceleration
  • PCIe Gen 4 (Root Complex)
  • PCle engine with support for multiple services including Non-Transparent Bridge (NTB)

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Training Presentation (9)

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Hardware

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