S32N7 Super-Integration Processor for Software-Defined Vehicles

  • This page contains information on a preproduction product. Specifications and information herein are subject to change without notice. For additional information contact support or your sales representative.

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Block Diagram

S32N7 Features

S32N7 Block Diagram

Features

Processors

  • Up to 8x split-lock Arm® Cortex®-A78AE cores operating at up to 1.8 GHz
  • Up to 12x split-lock Arm® Cortex®-R52 cores operating at up to 1.4 GHz
  • RISC-V-based accelerator for networking, math and data intensive workloads
  • eIQ® Neutron neural processing unit (NPU) for vehicle core NeuroNetwork offload
  • Independent safe system manager
  • Independent safe communication manager
  • Independent housekeeping controller

Low-Power Modes

  • Up to 5x power modes supporting always-ON, ultra low-power and AI-enabled low-power operation capabilities
  • Suspend to RAM support
  • Periodic wake support

Memory

  • Up to 2x LPDDR4X/5/5X DRAM interfaces
  • Up to 36 MB platform SRAM
  • 2x channel NVM interface supporting serial, quad and octal NOR memory
  • 1x UFS 3.1 interface
  • eMMC 5.1 NAND flash and SD Card/SDIO flash support

Application Integration

  • Full on-chip hardware isolation and virtualization for isolated, mixed-criticality applications
  • Core-to-pin virtual hardware isolation technology supports freedom from interference

Functional Safety

  • Independent system manager handles the functional safety across all SOC partitions
  • Hardware provides freedom from interference and virtualized Quality of Service (QoS) mechanisms for shared resources
    • Keeps fault impact at the integrated ECU level with local reactions
    • Runtime operating mode, safe stop and reset all controlled individually for each integrated ECU, reducing the number of faults that lead to SoC reset
  • Processor developed according to processes that are certified to ISO 26262 for ASIL D functional safety

Security

  • The integrated HSE2 security engine provides advanced, future-proof security capabilities and high performance, enabling a postquantum hardware root-of-trust, fast secure boot, secure debug and secure update; real-time, high-speed message signing, authentication and encryption for secure communications; and more
    • Secure boot, security services and key management
  • Public key infrastructure and side-channel attack resistance
  • Distributed security approach to provide increased availability of security services, increased parallelism of security operations, clearer prioritization between tasks and minimizes latency
  • Developed according to cybersecurity processes that are certified to ISO/SAE 21434, UN R155 and also targeted for SESIP Level 2 certification
  • Up to 2x asymmetric crypto accelerators support secure communications and secure OTA updates
  • Up to 2x symmetric accelerator in-vehicle communications

Communication and Networking

  • An independent communication subsystem manages low-speed communication interfaces
  • CAN Hub virtualizes CAN I/O and allows applications to share CAN I/O pins, allows CAN frames to be routed to multiple CAN controllers and offloads CAN-to-CAN routing from the host core
  • Multiple CAN FD, CAN XL, LIN and FlexRay® interfaces
  • Integrated Time-Sensitive Networking (TSN) Ethernet switch supporting interfaces speeds between 10Mbps to 10Gbps
  • Per-port In-line encryption with MACsec acceleration
  • PCI Express Gen 4 (Root Complex)
  • PCle engine with support for multiple services including Non-Transparent-Bridge (NTB)

Documentation

Quick reference to our documentation types

Support

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