Secure HS-CAN Transceiver with Sleep Mode

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Product Details

Block Diagram

TJA1153 Application Block Diagram

TJA1153 Application Block Diagram



  • The TJA1153A is a secure HS-CAN transceiver with Sleep mode and a VIO supply pin. The VIO pin allows for direct interfacing with 3.3 V and 5 V microcontrollers
  • ISO 11898-1:2015, ISO 11898-2:2016 and SAE J2284-1 to SAE J2284-5 compliant
  • Operates in classical CAN and CAN FD systems with arbitration phase bit rate set at 125 kbit/s, 250 kbit/s or 500 kbit/s
  • For arbitration bit rates of 250 kbit/s and 500 kbit/s, the fast phase bit rate can be set to two or four times the arbitration bit rate
  • AEC-Q100 Rev-G qualified (grade 1)
  • Low electromagnetic emission (EME) and high electromagnetic immunity (EMI)
  • HVSON14 plastic small outline package

System Control and Diagnostic Features

  • Mode control via dedicated control pins EN and STB_N
  • Overtemperature shutdown

Security Features

  • Spoofing protection
  • Flooding protection
  • Tamper protection

Predictable and Fail-Safe Behavior

  • Functional behavior predictable under all supply conditions
  • Transceiver disengages from bus when not powered (zero load)
  • Transmit data (TXD) dominant time-out function
  • Internal biasing of TXD, EN and STB_N input pins


  • High ESD handling capability on the bus pins (8 kV HBM)
  • Bus and VBAT pins protected against transients in automotive
  • Undervoltage detection on pins VCC, VIO and VBAT
  • Thermally protected

Product Programs

EdgeLock® Assurance

The TJA1153, part of the EdgeLock Assurance program, is designed to meet industry standards and follows NXP's security-by-design approach.


Quick reference to our documentation types.

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