8-bit S08RC, S08RD, S08RE and S08RG MCUs

Overview

The S08R family offers an upward migration path from NXP^®.s 68HC05 and 68HC08 architectures for applications that need lower power, more peripherals and higher performance that the enhanced S08 core offers. This family is complemented by the S08RC, S08RD, S08RE and S08RG families.

Other features, depending on family member, include a carrier modulation timer for infrared remote control communications, a serial communications interface (SCI), serial peripheral interface (SPI), an analog comparator and two programmable timer channels.

Features

8-bit HCS08 CPU Core

Low-power technology
- Multiple power management modes including 100 nA powerdown
- Optional autowake-up from Stop 2 or Stop 3 modes with internal timer that typically requires only 300 nA additional current
- 1.8V operation
High performance when needed
- 125 µs minimum instruction cycle time down to 1.8V at 8 MHz bus
C-optimized architecture with multiply and divide instructions

On-Chip Debug Interface

Single-wire background debug module (BDM)
On-chip trace buffer with nine flexible trigger modes and multiple hardware breakpoints
Nonintrusive emulation

Integrated Third-Generation Flash Memory

In-application reprogrammable
- Self-timed, fast programming
- Fast Flash page erase: 20 µs (512B)
Can program 8 bits in 20 µs while in burst mode
10K write/erase cycles minimum (100K typical)
15-year minimum data retention; 100 years typical
Internal program/erase voltage generation
Flash granularity: 512B Flash erase/ 2B Flash program
Flexible block protection and security

Carrier Modulation Timer

Consists of a carrier generator, modulator and transmitter, which generate infrared pulses

Timer with Two Programmable Channels

Each channel programmable for
- Input capture, output compare or buffered pulse-width modulation (PWM)
- PWM can be edge- or center-aligned

Up to two Serial Communications Interfaces

One asynchronous serial communications interface (SCI)
- Flexible 13-bit modulo-based baud rate generator
- Double-buffered receive and transmit

Analog Comparator

Full rail-to-rail supply operation
Selectable interrupt on rising edge, falling edge, or either rising or falling edge of comparator output
Option to compare unknown input to a fixed internal bandgap reference voltage or external user-supplied reference

System Protection

Selectable low-voltage detect/reset at nominal 1.8V
Low-battery warning
Computer operating properly (COP) watchdog timer

Up to 39 Input/Output (I/O) Lines

Programmable pull-ups
High-current drivers
Eight keyboard interrupts