PowerQUICC® Processor with CPM (2 SCC, 1 SMC), 10/100 Ethernet

Product Details

Block Diagram



  • Maximum frequency operation of the external bus is 66 MHz in 1:1 mode
  • Single-issue, 32-bit core (compatible with Power Architecture technology) with 32, 32-bit general-purpose registers (GPRs)
  • Up to 32-bit data bus (dynamic bus sizing for 8, 16, and 32 bits)
  • 32 address lines
  • Memory controller (eight banks)
  • General-purpose timers
  • System integration unit (SIU)
  • Interrupts
  • Communications processor module (CPM)
  • Two baud rate generators
  • Two SCCs (serial communication controllers) (10BaseT Ethernet, HDLC, Transparent)
  • One SMC (serial management channel)
  • One SPI (serial peripheral interface)
  • Fast Ethernet controller (FEC)
  • PCMCIA interface
  • Debug interface
  • 1.8 V Core and 3.3 V I/O operation with 5-V TTL compatibility
  • 256-pin, 23*23 1.27 ball pitch (BGA) package

Comparison Table

MPC866 Family Versions and Masks

Qual Process Mask IMMR [16:31]
Rev 0.3 MC HiP6W 3L90H 0x0800
Rev A.0 MC HiP6W 0L96R 0x0801
Note 1: Where nn = 50, 66, 100, or 133


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Design Resources


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1 software file

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