S32R26 and S32R27 Microcontrollers for High-Performance Radar

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Product Details

Block Diagram

S32R2x Block Diagram

S32R2x Block Diagram

Features

  • S32R264 and S32R274 shared features:
    • Dual Power Architecture® e200z7 32-bit CPU
    • Dual Power Architecture e200z4 32-bit CPU with checker core (available in lock-step operation)
    • 2 MB Flash with ECC
    • 1.5 MB SRAM with ECC
    • Radar Signal Processing Toolbox (SPT 2.0)
    • Radar interfaces: MIPI-CSI2 (4 data lanes)
    • Safety: ISO 26262 SEooC up to ASIL D
    • Security: CSE2 (Cryptographic Services Engine)
    • -40 to 150˚ C (junction) temperature
    • Interfaces: Zipwire, 2x SAR-ADC, 2x SPI, 2x I2C, 3x FlexCAN (including 2x CAN FD), Flexray, LINFlexD, Ethernet
  • S32R264 specific features:
    • AFEPLL
    • Improved EMC performance in the GLONASS band (when using S32R264)
  • S32R274 specific features:
    • SDPLL
    • Radar interfaces: ΣΔ-ADC (4x 12-bit,10 MSps) and DAC (10 MSps)

SafeAssure

SafeAssure Functional Safety Program

SafeAssure Functional Safety Program

When it comes to functional safety, NXP stands for quality and reliability. Our SafeAssure program simplifies system-level safety requirements in accordance with ISO 26262.
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