Microcontrollers for Optimized Radar

  • Instead, use the S32R294 MCUs, designed to extend the existing S32R product family that already includes the MPC5775K, S32R274 and the S32R372 devices. If you are still interested in S32R37 MCUs, please contact NXP support.

Click over video to play

Block Diagram

S32R37 Radar MCU

S32R37 Block Diagram



  • Dual issue computation cores: Power Architecture® e200z7 32-bit CPU
  • 1.2 MB on-chip code flash memory (FMC flash memory) with ECC
  • 1 MB on-chip SRAM with ECC

RADAR processing

  • Signal Processing Toolbox (SPT) for RADAR signal processing acceleration
  • Cross Triggering Engine (CTE) for precise timing generation and triggering
  • MIPICSI2 interface to connect external RADAR RX ADCs

Memory protection

  • Each core memory protection unit provides 24 entries
  • Data and instruction bus system memory protection unit (SMPU) with 16 region descriptors each
  • Register protection

Functional safety

  • Enables ASIL-B applications
  • Fault Collection and Control Unit (FCCU) for fault collection and fault handling
  • Memory Error Management Unit (MEMU) for memory error management
  • Safe eDMA controller
  • Self-Test Control Unit (STCU2)
  • Error Injection Module (EIM)
  • On-chip voltage monitoring
  • Clock Monitor Unit (CMU)


  • Cryptographic Security Engine (CSE2)
  • Supports censorship and life-cycle management

Part numbers include: FS32R372SAK0MMM.


Quick reference to our documentation types.

1-5 of 11 documents

Show All

Design Files

Quick reference to our design files types.

1 design file


Quick reference to our board types.

1-5 of 7 hardware offerings

Show All


Quick reference to our software types.

1-5 of 6 software files

Show All

Note: For better experience, software downloads are recommended on desktop.

Engineering Services

4 engineering services

To find additional partner offerings that support this product, visit our Partner Marketplace.


5 trainings


What do you need help with?