EL2 Monitor Partitioning Hypervisor for Arm® Cortex®-R52 (EL2M)

EL2M

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Exception Level 2 (EL2) Monitor is NXP's lightweight partitioning hypervisor built for Arm® Cortex®-R52 cores and certified to ASIL D—the highest automotive safety level. It delivers robust isolation so each software component runs securely and independently. With its minimal footprint and tight integration with NXP hardware, EL2 Monitor delivers unmatched safety, efficiency and reliability.

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EL2 Monitor Paravirtualization Diagram

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EL2 Monitor Trap and Emulation Diagram

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Features

Partitioning

  • Isolated R52 Partitions: Securely separates the Embedded Execution Environment (EENV) into independent Arm Cortex-R52 partitions using EL2 microprocessor (MPU) programming and Generic Interrupt Controller (GIC) Distributor emulation/paravirtualization
  • MRU Channel Isolation: Within an R52 partition, MRU channels are isolated between software entities running at lower privilege levels, ensuring each entity can only access its pre-assigned channels through dedicated virtualized MRU instances
  • Hardware-Level Memory Protection: EL2 MPU enforces strict memory boundaries, adding a critical layer of defense, even if an exception level 1 (EL1) guest OS is compromised

Trap, Emulation and Paravirtualization

  • Transparent Interrupt Handling: Traps and emulates GIC Distributor access so EL1 applications remain hypervisor-agnostic, with access operations completing in under 3 microseconds
  • Paravirtualization via Cortex Microcontroller Software Interface Standard (CMSIS) APIs: Provides ready-to-use Arm CMSIS GIC Driver APIs, achieving half the latency of full emulation and reducing development time and memory usage while improving performance to under 1.5 microseconds
  • MRU Virtualization: Within an R52 partition, each software entity accesses the MRU through its own virtualized instance, with handlers servicing measured in under 1.5 microseconds:
    • Trap and Emulate Mode: Applications use hypervisor APIs to reserve/free channels, while actual channel access is transparently trapped and emulated
    • Paravirtualized Mode (future): Fully paravirtualized MRU access through optimized APIs for enhanced performance

Supported Devices

  • S32K5: S32K5 Automotive Microcontrollers
  • S32N5: S32N5 Vehicle Super-Integration Processor
  • S32J100: S32J100 High-Performance Ethernet Switch and Network Controller
  • S32E2: S32E2 Safe and Secure High-Performance Real-Time Processors with Actuation Support
  • S32N7: S32N7 Super-Integration Processor for Software-Defined Vehicles
  • S32Z2: S32Z2 Safe and Secure High-Performance Real-Time Processors

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  • Software Development Resources

    IPCF for S32K5

    FLEXERARev 1.0Mar 31, 2026 12:33:00SW32K5-STD-L
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