Layerscape LS1024A Reference Design Board

LS1024A-RDB

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Product Details

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Block Diagram

Layerscape LS1024A

LS1024RDB System Block Diagram

Features

Processor

  • Single or dual Arm® Cortex®-A9 SMP/AMP 32-bit cores, with NEON DSP and FPU, up to 1.2 GHz
  • 32 kB instruction and data caches
  • 256 kB shared L2 cache

Memory

  • Default 256MB DDR3 (Support for 512MB DDR3)
  • 64MB NOR flash
  • 2GB NAND Flash
  • 64MB SPI Nor FLASH
  • 64KB I2C EEPROM

Ethernet

  • 4x GbE LAN connectors
  • 2x GbE WAN connector
  • 1x SFP+ connector

Basic Peripherals and Interconnect

  • 4 PORT SMSC USB3.0 HUB
    • 2x USB TYPE 3.0A Connectors
  • 2 Mini PCI EXPRESS Connectors
  • 1 PORT USB2.0 Controller
  • 1 UAB TYPE 2.0A Connector
  • SERDES
    • 1x PCI EXPRESS
    • 2x Mini PCI Express Connectors
    • 2x SATA Connectors
  • DECT
    • One Adaptor Socket onboard
  • Voice
    • 2 FXS Ports (ZL88601 Dual Wide Band SLIC)
  • UART
    • UART0 is connected to onboard DB9 connector
    • UART1 is brought to 5-pin connector
  • EXPANSION 128 Pin High-Density Connector
    • Expansion Bus
    • SPI Bus
    • TDM Bus
    • I2C-bus
    • UART Busses
    • GPIO
    • System and External Reset
    • Power
  • LCD Connector
    • Expansion Bus
    • SPI Bus

Additional Features

  • PMIC for voltage control

Buy Options

  • $2000.00 USD
  • For a quantity of 1
    • Availability: In stock
    • Inventory: 2
    • Shipping: Normally ships 1-2 business days
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Design Resources

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Documentation

Quick reference to our documentation types.

2 documents

Design Files

1 design file

Software

2 software files

Note: For better experience, software downloads are recommended on desktop.

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