DSCs with Integrated FPU and Trigonometric Math Engine with OPAMP and Quadrature Decoder


Roll over image to zoom in

Product Details

Select a section:

Block Diagram

MC56F80xxx MCUs

MC56F80xxx MCUs


Processor Complex

  • 100 MHz 56800EF DSP core
    • Enhanced single-precision Floating Point math Unit (eFPU)
    • Coordinate Rotation Digital Compute (CORDIC) engine
  • JTAG/EOnCE debug controller


  • 64kB Flash
  • 8kB SRAM

System Control

  • Intermodule crossbar (support flexible connection among peripherals or GPIOs)
  • Event Generator (support and/or/nor/xor logic operation and multiple trigger modes)
  • Enhanced DMA (support minor and major loop, more flexible data transition and less CPU intervention)
  • Memory resource protection
  • LVI, POR and brownout reset
  • CRC
  • Internal and external watchdog


  • Eight channels 312ps high-resolution PWM
  • 1x Quad Timer to support four-channel capture
  • 1x Quadrature Decoder
  • 3x 32-bit PIT


  • 2x 12-bit ADC each w/ x2/4 PGA, each up to 1.6MSps sample rate
  • 2x Operational Amplifier, 8MHz GBP, support up to x16 PGA mode
  • 3x Analog Comparator each w/ 8-bit DAC


  • 1x LPI2C, support full PMBus
  • 1x SPI
  • 2x UART


  • LQFP64
  • LQFP48
  • LQFP32
  • QFN32


  • -40 to 125°C


  • MC56F80000-EVK - can connect with low-voltage FRDM-LV driver board
  • HVP-56F80748 EVK - can connect with high-voltage HVP-MC3PH driver board
  • Motor control and digital power reference designs
  • CodeWarrior IDE
  • Software Development Kit (SDK)
  • GUI Config Tools (Pin, Clock, Peripherals)
  • FreeMaster debug tool
  • PEMicro Multilink and Cyclone support


  • IEC60730 Class B Certification
  • AEC-Q100


Quick reference to our documentation types.

1-5 of 11 documents

Show All

Design Resources

Select a section:


3 hardware offerings


1-5 of 6 software files

Show All

Note: For better experience, software downloads are recommended on desktop.