High-Performance Six-Core DSP

Product Details

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Block Diagram

MSC8256 High-Performance Six-Core DSP Block Diagram

MSC8256 High-Performance Six-Core DSP Block Diagram

Features

  • Six StarCore® DSP SC3850 core subsystems each with:
    • SC3850 DSP core at up to 1 GHz
    • 512 KB unified L2 cache/M2 memory
    • 32 KB I-cache, 32 KB D-cache
    • Fully programmable 1056 KB M3 shared memory (SRAM)
  • Two DDR 2/3 64-bit SDRAM interfaces at up to 800 MHz data rate
  • Chip-level arbitration and switching fabric, non-blocking, fully pipelined, low-latency
  • High-speed interconnects
    • Dual 4x/1x Serial RapidIO at 1.25/2.5/3.125 Gbaud
    • PCI Express 4x/1x
    • Two SGMII
  • Dual RISC QUICC Engine® supporting
    • RGMII gigabit Ethernet ports
    • Serial peripheral interface (SPI)
  • TDM highway 1024 ch., 400 Mbps, divided into four ports of 256
  • DMA engine 16 bi-directional channels
  • Other peripheral interfaces
    • UART
    • I²C
    • 32 GPIO
    • 16 timers
  • Technology
    • Process: 45 nm SOI
    • Voltage: 1-volt core, 2.5, 1.8/1.5-volt I/O
    • Package: FC-BPGA (29 x 29) 1-mm pitch, RoHS
  • This product is included in NXP®.s product longevity program, with assured supply for a minimum of 10 years after launch

Documentation

Quick reference to our documentation types.

1-5 of 50 documents

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Design Resources

Hardware

2 hardware offerings

  • Test Accessories and Debugger

    TRACE32 JTAG Debugger for StarC

  • Complementary Silicon or Component

    Low Power DRAM

Software

1 software file

Note: For better experience, software downloads are recommended on desktop.

Engineering Services

1-5 of 6 engineering services

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To find a complete list of our partners that support this product, please see our Partner Marketplace.

Training

2 trainings

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