Multimode, multichannel decoder software functionality
Dolby and/or DTS license required
Digital Signal Processing Core
1.25 V core with a 3.3 V peripheral I/O.
150 Million Instructions Per Second
(MIPS) with a 150 MHz clock at an internal logic supply (QVDDL) of 1.25V (0
deg C to 70 deg C for consumer-grade devices; -40 deg C to 85 deg C for
Object Code Compatible with the DSP56000 core with highly parallel
Data ALU with a 24 x 24 bit multiplier-accumulator and a 56-bit barrel
shifter. 16-bit arithmetic support
Program Control with position independent code support and instruction cache
- Six-channel DMA controller
Low jitter, PLL based clocking with a wide range of frequency
multiplications (1 to 1024), predivider factors (1 to 32) and power saving
clock divider (2i: i=0 to 7). Reduces clock noise
Internal address tracing support and OnCE for Hardware/Software debugging
- JTAG port
Very low-power CMOS design, fully static design with operating frequencies
down to DC
- STOP and WAIT low-power standby modes
On-chip Memory Configuration
- 4K - 6Kx24 Bit Y-Data RAM and 4Kx24 Bit Y-Data ROM.
- 4K - 10Kx24 Bit X-Data RAM and 4Kx24 Bit X-Data ROM.
20Kx24 Bit Program and Bootstrap ROM including a PROM patching mechanism.
- 2K - 10Kx24 Bit Program RAM.
- Various memory switches available
Enhanced Serial Audio Interface (ESAI): up to 4 receivers and up to 6
transmitters, . I2S, Sony, AC97, network and other
Enhanced Serial Audio Interface I (ESAI_1): up to 4 receivers and up to 6
transmitters, leader or follower. I2S, Sony, AC97, network and other
programmable protocols. Note 80 pin package only.
Serial Host Interface (SHI): SPI and I2C protocols, multi controller
capability in I2C mode, 10-word receive FIFO, support for 8, 16 and 24-bit
- Triple Timer module (TEC).
- Hardware Watchdog Timer.
Most pins of unused peripherals may be programmed as GPIO lines. Up to 47
pins can be configured as GPIO on the 80-pin package and 20 pins on the