High-Performance Six-Core DSP

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Block Diagram

MSC8156 High-Performance Six-Core DSP Block Diagram

MSC8156 High-Performance Six-Core DSP Block Diagram

Features

  • Six StarCore® DSP SC3850 core subsystems each with:
    • SC3850 DSP core at up to 1 GHz
    • 512 KB unified L2 cache/M2 memory
    • 32 KB I-cache, 32 KB D-cache
    • Fully programmable 1056 KB M3 shared memory (SRAM)
  • MAPLE-B - highly flexible programmable Turbo and Viterbi decoder supports configurable decoding parameters. It can perform up to 200 Mbps of Turbo decoding (six iterations) or up to 115 Mbps of K = 9 (zero tail) Viterbi decoding
  • Two DDR 2/3 64-bit SDRAM interfaces at up to 800 MHz data rate
  • Chip-Level Arbitration and Switching Fabric, non-blocking, fully pipelined, low latency
  • High-speed interconnects:
    • Dual 4x/1x Serial RapidIO at 1.25/2.5/3.125 Gbaud
    • PCI Express 4x/1x
    • Two SGMII
  • Dual RISC QUICC Engine® supporting:
    • RGMII gigabit Ethernet ports
    • Serial peripheral interface (SPI)
  • TDM highway 1024 ch., 400 Mbps, divided into four ports of 256
  • DMA engine 16 bi-directional channels
  • Other peripheral interfaces:
    • UART
    • I²C
    • 32 GPIO
    • 16 timers
  • Technology
    • Process: 45 nm SOI
    • Voltage: 1-volt core, 2.5, 1.8/1.5-volt I/O
    • Package: FC-BPGA (29x29) 1 mm pitch, RoHS
  • This product is included in NXP®.s product longevity program, with assured supply for a minimum of 10 years after launch

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Documentation

Quick reference to our documentation types.

1-10 of 66 documents

Compact List

Application Note (36)
Application Note Software (13)
Brochure (1)
Data Sheet (1)
Fact Sheet (3)
Package Information (1)
Product Brief (1)
Reference Manual (6)
Selector Guide (1)
Technical Notes (2)
User Guide (1)

Design Files

Hardware

Quick reference to our board types.

1 hardware offering

Software

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1 software file

Note: For better experience, software downloads are recommended on desktop.

Engineering Services

5 engineering services

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