High-Performance Six-Core DSP

MSC8156

The MSC8156 is based on the industry's highest-performance DSP core built on StarCore® technology and designed for the advanced processing requirements and capabilities of today's high-performance applications for the wireless broadband, medical imaging, aerospace, defense and advanced test and measurement markets. It delivers higher performance and power savings, leveraging 45 nm process technology in a highly integrated system-on-chip (SoC) to provide performance equivalent to a 6 GHz single-core device. The MSC8156 helps equipment manufacturers create end products and services that integrate more functionality in a smaller hardware footprint.

The MSC8156 DSP delivers a high level of performance and integration, combining six fully programmable enhanced SC3850 DSP cores, each running at up to 1 GHz. Developed by NXP® and integrated on-chip, the MAPLE-B accelerator supports hardware acceleration for Turbo and Viterbi channel decoding and for DFT/iDFT and FFT/iFFT algorithms. A high-performance internal RISC-based QUICC Engine® subsystem supports multiple networking protocols to guarantee reliable data transport over packet networks while significantly offloading processing from the DSP cores.

The MSC8156 embeds large internal memory and supports a variety of advanced high-speed interface types, including two RapidIO® interfaces, two gigabit Ethernet interfaces for network communications, a PCI Express® controller, two DDR controllers for high-speed, industry standard memory interface and four multi-channel TDM interfaces. The MSC8156 allows a high degree of scalability through pin compatibility with all MSC825x and MSC815x DSP devices.

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Block Diagram

MSC8156 High-Performance Six-Core DSP Block Diagram

MSC8156 High-Performance Six-Core DSP Block Diagram
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Features

  • Six StarCore® DSP SC3850 core subsystems each with:
    • SC3850 DSP core at up to 1 GHz
    • 512 KB unified L2 cache/M2 memory
    • 32 KB I-cache, 32 KB D-cache
    • Fully programmable 1056 KB M3 shared memory (SRAM)
  • MAPLE-B - highly flexible programmable Turbo and Viterbi decoder supports configurable decoding parameters. It can perform up to 200 Mbps of Turbo decoding (six iterations) or up to 115 Mbps of K = 9 (zero tail) Viterbi decoding
  • Two DDR 2/3 64-bit SDRAM interfaces at up to 800 MHz data rate
  • Chip-Level Arbitration and Switching Fabric, non-blocking, fully pipelined, low latency
  • High-speed interconnects:
    • Dual 4x/1x Serial RapidIO at 1.25/2.5/3.125 Gbaud
    • PCI Express 4x/1x
    • Two SGMII
  • Dual RISC QUICC Engine® supporting:
    • RGMII gigabit Ethernet ports
    • Serial peripheral interface (SPI)
  • TDM highway 1024 ch., 400 Mbps, divided into four ports of 256
  • DMA engine 16 bi-directional channels
  • Other peripheral interfaces:
    • UART
    • I²C
    • 32 GPIO
    • 16 timers
  • Technology
    • Process: 45 nm SOI
    • Voltage: 1-volt core, 2.5, 1.8/1.5-volt I/O
    • Package: FC-BPGA (29x29) 1 mm pitch, RoHS
  • This product is included in NXP®.s product longevity program, with assured supply for a minimum of 10 years after launch

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