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Development Boards and Designs
Development Boards and Designs
TRK-S12ZVL:StarterTRAK Development Board for MagniV S12ZVL MCU for LIN Applications
DEVKIT-ZVL128:Development Board for S12ZVL128 MCU Evaluation
DEVKIT-S12ZVL:Development Board for 9S12ZVL32 MCU Evaluation 
S12ZVL32 RGB LED Lighting Reference Design
S12ZVL and NCx3320 NFC Door Handle solution.
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CodeWarrior for MCU 10.6
To setup your CodeWarrior development environment for S12 MagniV mixed-signal microcontroller applications.
- Read the document below for download and installation instructions.
- Download and install the CW MCU v10.6 product.
- Download and install CW MCU v10.6 Update 1.0.0.
SafeAssure Functional Safety Program
When it comes to functional safety, NXP stands for quality and reliability. Our SafeAssure program simplifies system-level safety requirements in accordance with ISO 26262.
Read more
Comparison Table
S12ZVL Family Comparison
| 48-LQFP | ||||||||||
|---|---|---|---|---|---|---|---|---|---|---|
| S12ZVLA | S12ZVL | S12ZVL | ||||||||
| Memory | Flash [kB] | 128 | 96 | 64 | 128 | 96 | 64 | 32 | 16 | 8 |
| EEPROM [kB] | 2 | 1 | 2 | 1 | 0.128 | |||||
| RAM [kB] | 8 | 4 | 8 | 4 | 1 | 0.5 | ||||
| UHV | V reg | 5V / 3.3V ; 70mA or up to 170 (with ballast option / BCTL) |
5V; 70mA or up to 170 (with ballast option / BCTL) |
|||||||
| V reg tolerance | 2% | 3% | 3% | |||||||
| PHY | LIN | |||||||||
| HVI | 1 | |||||||||
| Analog | ADC (LB) channel | 10 | ||||||||
| ADC (LB) resolution | 12 Bit | 10 Bit | 10 Bit | |||||||
| ACMP with 8bit DAC | 1 | - | - | |||||||
| PGA | 1 | - | - | |||||||
| PGA levels | 10/20/40/80x | - | - | |||||||
| Comms | SCI | 2 | ||||||||
| SPI | 1 | |||||||||
| IIC | 1 | |||||||||
| MSCAN | 1 | - | ||||||||
| Tim | Timer (6+2ch) | 6ch + 2ch (16 Bit) | ||||||||
| PWM | 8ch 8Bit (or 4ch 16Bit) | |||||||||
| I/O | GPIO | 35 | - | |||||||
| intrr. Cap. IO (5/12v) | 22/1 | |||||||||
| eVdd (5V/20mA) | 1 | |||||||||
| N-GPIOs (5V / 25mA) | 3 | 1 | ||||||||
| Temperature options | C / V / M | C / V / M | ||||||||
| 32-LQFP | 32-QFN | 32-LQFP | 32-QFN | ||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| S12ZVLA | S12ZVL | S12ZVLA | S12ZVL | S12ZVLS | |||||||||||
| Memory | Flash [kB] | 128 | 96 | 64 | 128 | 96 | 64 | 128 | 96 | 64 | 32 | 16 | 8 | 32 | 16 |
| EEPROM [kB] | 2 | 1 | 2 | 1 | 2 | 1 | 0.128 | ||||||||
| RAM [kB] | 8 | 4 | 8 | 4 | 8 | 4 | 1 | 0.5 | 1 | ||||||
| UHV | V reg | 5V / 3.3V ; 70mA or up to 170 (with ballast option / BCTL) |
5V; 70mA or up to 170 (with ballast option / BCTL) |
||||||||||||
| V reg tolerance | 2% | 3% | 2% | 3% | |||||||||||
| PHY | LIN | ||||||||||||||
| HVI | 1 | ||||||||||||||
| Analog | ADC (LB) channel | 6 | 7 | 6 | |||||||||||
| ADC (LB) resolution | 12 Bit | 10 Bit | 12 Bit | 10 Bit | |||||||||||
| ACMP with 8bit DAC | 1 | 0 | 1 | - | |||||||||||
| PGA | 1 | - | 1 | - | |||||||||||
| PGA levels | 10/20/40/80x | - | 10/20/40/80x | - | |||||||||||
| Comms | SCI | 2 | |||||||||||||
| SPI | 1 | ||||||||||||||
| IIC | 1 | ||||||||||||||
| MSCAN | 1 | - | |||||||||||||
| Tim | Timer (6+2ch on silicon) | 6ch + 2ch (16 Bit) | |||||||||||||
| PWM | 8ch (16Bit) | 8ch 8Bit (or 4ch 16Bit) | |||||||||||||
| I/O | GPIO | 20 | |||||||||||||
| intrr. Cap. IO (5/12v) | 16/1 | ||||||||||||||
| eVdd (5V/20mA) | 1 | ||||||||||||||
| N-GPIOs (5V / 25mA) | 1 | 1 | 3 | ||||||||||||
| Temperature options | C / V / M | C / V / M | |||||||||||||