Integrated ColdFire® Microprocessor with DMA

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Block Diagram

Integrated ColdFire MCF5206E Microprocessor with DMA Block Diagram

Integrated ColdFire<sup>&#174;</sup> MCF5206E Microprocessor with DMA Block Diagram


  • ColdFire® V2 Core
  • MAC and divide unit
  • 4 KB direct-mapped instruction cache
  • 8 KB on-chip SRAM
  • DRAM controller, supports EDO and page node DRAMs
  • 2-channel DMA controller
  • Two universal synchronous/asynchronous receiver/transmitters (UART)
  • Dual 16-bit general-purpose multimode timers
  • I²C compatible bus
  • System interface
  • System debug support
  • Fully static 3.3-volt operation with 5-volt tolerant inputs
  • 160-pin QFP package pin-compatible with MCF5206
  • 8-bit general purpose parallel I/O port
  • 50 MIPS at 54 MHz
  • Available at 40 and 50 MHz

Part numbers include: MCF5206EAB40, MCF5206EAB54, MCF5206ECAB40.


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