Integrated ColdFire® V4 Microprocessor

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Block Diagram

ColdFire MCF540X Microprocessor Block Diagram

ColdFire MCF540X Microprocessor Block Diagram


  • ColdFire® V4 core-delivering up to 316 (Dhrystone 2.1) MIPS @ 220 MHz
  • Harvard memory architecture and branch cache acceleration logic
  • Fully code compatible with V2 and V3 ColdFire cores
  • 16 KB instruction-cache, 8 KB data-cache
  • 4 KB SRAM
  • Multiply-accumulate (MAC) with integer and fractional capabilities
  • Hardware integer divide unit
  • Integrated pheripherals
    • DRAM controller: glueless interface to SDRAM or ADRAM
    • Two universal asynchronous receiver/transmitter (UARTS), one that supports synchronous operations
    • Four fully programmable direct memory access (DMA) channels
    • Two 16-bit general-purpose timers
    • I²C module
    • Parallel I/O interface
    • System integration module(SIM)
  • Pin-compatible with MCF5307


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Design Files

1 design file

  • Models

    Core Model For MicroAPL Limited's Emulation Library


2 hardware offerings


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Note: For better experience, software downloads are recommended on desktop.


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