Integrated ColdFire® V4 Microprocessor

MCF540X
  • Not Recommended for New Designs
  • This page contains information on a product that is not recommended for new designs.

The MCF5407 is the first standard microprocessor to implement the ColdFire® V4 core. Increasing the internal speed of the core allows higher performance and provides system designers with an easy-to-use lower speed system interface.

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Block Diagram

ColdFire MCF540X Microprocessor Block Diagram

ColdFire MCF540X Microprocessor Block Diagram
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Features

  • ColdFire® V4 core-delivering up to 316 (Dhrystone 2.1) MIPS @ 220 MHz
  • Harvard memory architecture and branch cache acceleration logic
  • Fully code compatible with V2 and V3 ColdFire cores
  • 16 KB instruction-cache, 8 KB data-cache
  • 4 KB SRAM
  • Multiply-accumulate (MAC) with integer and fractional capabilities
  • Hardware integer divide unit
  • Integrated pheripherals
    • DRAM controller: glueless interface to SDRAM or ADRAM
    • Two universal asynchronous receiver/transmitter (UARTS), one that supports synchronous operations
    • Four fully programmable direct memory access (DMA) channels
    • Two 16-bit general-purpose timers
    • I²C module
    • Parallel I/O interface
    • System integration module(SIM)
  • Pin-compatible with MCF5307

Key Parametrics

  • Status
    End of Life

Documentation

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Design Files

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  • Models

    Core Model For MicroAPL Limited's Emulation Library

    ZIPRev n/aOct 26, 20066.4 KBCF68KLIB
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Hardware

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