MPC860: MPC860 PowerQUICC^® Processor

Embedded MPC8xx Core with 88 MIPS at 66 MHz (using Dhrystone 2.1); MPC860P - 106 MIPS at 80 MHz for the MPC860P

• 4Kb Instruction Cache; MPC860P - 16Kb Instruction Cache
• 4Kb Data Cache; MPC860P - 8Kb Data Cache
• 8Kb Dual Port RAM
• Instruction and Data MMUs
• Up to 32-Bit Data Bus (Dynamic Bus Sizing for 8,16, and 32 Bits)
• 32 Address Lines
• Complete Static Design (040 MHz Operation)
• Memory Controller (Eight Banks)
• General-Purpose Timers
• System Integration Unit (SIU)
• Interrupts
• Communications Processor Module (CPM)
• Four Baud Rate Generators
• Four SCCs (Serial Communication Controllers)
• Two SMCs (Serial Management Channels)
• One SPI (Serial Peripheral Interface)
• One I²C (Inter-Integrated Circuit) Port
• Time-Slot Assigner
• Parallel Interface Port
• PCMCIA Interface
• Low Power Support
• Debug Interface
• 3.3 V Operation with 5V TTL Compatibility