PowerQUICC® Processor with CPM (1 SCC, 1 SMC), 10/100 Ethernet



  • Single-issue, 32-bit version of the core (compatible with Power Architecture technology) with 32, 32-bit general-purpose registers (GPRs)
  • The MPC859DSL provides enhanced ATM functionality over that of the MPC860SAR. The MPC859DSL adds major new features available in "enhanced SAR" (ESAR) mode, including the following:
    • Multiple APC priority levels available to support a range of traffic pace requirements
    • Port-to-port switching capability without the need for RAM-based microcode
    • Simultaneous MII (100Base-T) and UTOPIA (half-duplex) capability
    • Parameter RAM for both SPI and I2C can be relocated without RAM-based microcode
    • Supports full-duplex UTOPIA leader (ATM side) operation using a "split" bus
  • Up to 32-bit data bus (dynamic bus sizing for 8, 16, and 32 bits)
  • UTOPIA port supports up to 4 PHY addresses
  • Complete static design
  • Memory controller (eight banks)
  • General-purpose timers
  • Fast Ethernet controller (FEC)
  • System integration unit (SIU)
  • Interrupts
  • Communications processor module (CPM)
  • Four baud rate generators
  • One SCC (serial communication controller) for Ethernet (SCC1)
  • One SMC (serial management channel) for UART (SMC1)
  • One SPI (serial peripheral interface)
  • One I2C (inter-integrated circuit) port
  • Parallel interface port (PIP)
  • One PCMCIA socket (Port B)
  • Low power support
  • Debug interface
  • 1.8 V core, 3.3 V I/O
  • 357-pin PBGA package

Part numbers include: MPC859DSLCZP50A, MPC859DSLVR50A, MPC859DSLZP50A, MPC859PVR133A.

Comparison Table

MPC866 Family Versions and Masks

Qual Process Mask IMMR [16:31]
Rev 0.3 MC HiP6W 3L90H 0x0800
Rev A.0 MC HiP6W 0L96R 0x0801
Note 1: Where nn = 50, 66, 100, or 133


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