PowerQUICC® Processor with CPM (2 SCC, 1 SMC), 10/100 Ethernet

Overview

The MPC853T is an "ethernet-only" member of the MPC866 Family. Like the MPC866, the MPC853T is a 0.18 micron version of the PowerQUICC^® Family and can operate up to a maximum of 100 MHz on the MPC8xx Core with a maximum of 66 MHz external bus. The MPC853T has a 1.8 V core and has a 3.3 V I/O operation with 5 V TTL compatibilty. The MPC853T Integrated Communications Controller is a versatile one-chip integrated microprocessor and peripheral combination that can be used in a variety of controller applications. The MPC853T is ideal for voice-enabled systems (TDM-based) and ethernet to ethernet applications such as line cards.

The MPC853T is a Power Architecture-based derivative of NXP^® Semiconductors's Quad Integrated Communications Controller (PowerQUICC).. The CPU on the MPC853T is the MPC8xx core, a 32-bit microprocessor built on Power Architecture technology, incorporating memory management units (MMUs) and instruction and data caches.

Features

Maximum frequency operation of the MPC8xx core is 100 MHz

Maximum frequency operation of the external bus is 66 MHz in 1:1 mode
Single-issue, 32-bit core (compatible with Power Architecture technology) with 32, 32-bit general-purpose registers (GPRs)
Up to 32-bit data bus (dynamic bus sizing for 8, 16, and 32 bits)
32 address lines
Memory controller (eight banks)
General-purpose timers
System integration unit (SIU)
Interrupts
Communications processor module (CPM)
Two baud rate generators
Two SCCs (serial communication controllers) (10BaseT Ethernet, HDLC, Transparent)
One SMC (serial management channel)
One SPI (serial peripheral interface)
Fast Ethernet controller (FEC)
Time-slot assigner (TSA)
PCMCIA interface
Debug interface
1.8 V Core and 3.3 V I/O operation with 5-V TTL compatibility
256-pin, 23*23 1.27 ball pitch (BGA) package

Features

Maximum frequency operation of the MPC8xx core is 100 MHz

Maximum frequency operation of the external bus is 66 MHz in 1:1 mode
Single-issue, 32-bit core (compatible with Power Architecture technology) with 32, 32-bit general-purpose registers (GPRs)
Up to 32-bit data bus (dynamic bus sizing for 8, 16, and 32 bits)
32 address lines
Memory controller (eight banks)
General-purpose timers
System integration unit (SIU)
Interrupts
Communications processor module (CPM)
Two baud rate generators
Two SCCs (serial communication controllers) (10BaseT Ethernet, HDLC, Transparent)
One SMC (serial management channel)
One SPI (serial peripheral interface)
Fast Ethernet controller (FEC)
Time-slot assigner (TSA)
PCMCIA interface
Debug interface
1.8 V Core and 3.3 V I/O operation with 5-V TTL compatibility
256-pin, 23*23 1.27 ball pitch (BGA) package

MPC852TADS-KIT:MPC852T Application Development System Kit

Evaluation and Development Boards

	Qual	Process	Mask	IMMR [16:31]
Rev 0.3	MC	HiP6W	3L90H	0x0800
Rev A.0	MC	HiP6W	0L96R	0x0801

Qual

Process

Mask

IMMR [16:31]

Rev 0.3

HiP6W

3L90H

0x0800

Rev A.0

HiP6W

0L96R

0x0801

MPC853T: PowerQUICC® Processor with CPM (2 SCC, 1 SMC), 10/100 Ethernet

Overview

Features

Development Boards and Designs

Development Boards and Designs

Target Applications

Automotive

Communication Infrastructure

Mobile

Smart City

Comparison Table

MPC866 Family Versions and Masks

MPC853T: PowerQUICC^® Processor with CPM (2 SCC, 1 SMC), 10/100 Ethernet