PowerQUICC® II Processor with PCI, 128-ch. HDLC, 10/100 Ethernet

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  • This page contains information on a product that is not recommended for new designs.

Product Details

Block Diagram

MPC8250_BLKDIAG

Features

  • 300 MHz high-speed embedded G2 core
  • Powerful memory controller and system functions
  • Enhanced 32-bit RISC communications processor module
  • Up to two multiport 10/100 Mbps ethernet MAC
  • Up to two UTOPIA II ATM interfaces
  • Up to 128 HDLC channels (each channel 64 Kbps, full duplex)
  • Up to four 10 Mbps ethernet MAC
  • Strong 3rd-party tools support from 恩智浦合作伙伴计划 partner program members
  • Remote Access Concentrators
  • Regional Office Routers
  • Cellular Infrastructure equipment
  • Telecom Switching Equipment
  • Ethernet Switches
  • T1/E1-to-T3/E3 Bridges
  • xDSL Systems
  • Embedded G2 core at 300 MHz
    • 570 MIPS at 300 MHz (Dhrystone 2.1)
    • High-performance, superscalar microprocessor
    • Disable CPU mode
    • Supports the NXP® external L2 cache chip (MPC2605)
    • Improved low-power core
    • 16 Kbyte data and 16 Kbyte instruction cache
    • Memory Management Unit
    • Floating Point Unit
    • Common On-chip Processor (COP)
  • System Interface Unit (SIU)
    • Memory controller, including two dedicated SDRAM machines
    • PCI up to 66 MHz
    • Hardware bus monitor and software watchdog timer
    • IEEE 1149.1 JTAG test access port
  • High-Performance CPM with operating frequency of 133 MHz
    • Parallel I/0 registers
    • On-board 32 Kbytes of dual-port RAM
    • One multichannel controller (MCC), each supporting 128 full-duplex, 64 Kbps, HDLC lines
    • Virtual DMA functionality
    • Two FCCs supporting 10/100 Mbps Ethernet (up to two) (IEEE 802.3X with Flow Control)
    • Three MII interfaces
    • Four TDM interfaces (T1/E1) supporting four T1 lines or one T3 line
  • Two bus architectures: one 64-bit 60x bus and one 32-bit PCI or local bus
    • Integrated PCI interface
  • 1.8V or 2.0V internal and 3.3V I/O
  • 300 MHz power consumption: ~3 W
  • 480 TBGA package (37.5 x 37.5 mm)

Comparison Table

MPC8260 Derivatives

8250 8255 8260 8264 8265 8266
IMA Functionality - - - Yes - Yes
UTOPIA II Ports 0 2 2 2 2 2
PCI Interface Yes - - - Yes yes
Multi-Channel HDLC Up to 128 Up to 128 Up to 256 Up to 256 Up to 256 Up to 256
I-Cache (Kbyte) 16 16 16 16 16 16
Fast Communication Controllers (FCCs) 3 2 3 3 3 3
Serial Communications Controllers (SCCs) 4 4 4 4 4 4
D-Cache (Kbyte) 16 16 16 16 16 16
Ethernet (10/100) Up to 3 Up to 2 Up to 3 Up to 3 Up to 3 Up to 3
Ethernet (10T) Up to 4 Up to 4 Up to 4 Up to 4 Up to 4 Up to 4

PowerQUICC II Masks and Versions

IMMR_ [16-31]1 Rev_Num2 Qualification Revision Process Mask
MPC8260 Family XC A.1
B.3
C.2
0.29 µm
(HiP3)
0K26N
3K23A
6K23A, 7K23A
MPC8260 Family XC
MC
MC
A.0
B.1
C.0
0.25 µm
(HiP4)
2K25A
4K25A
5K25A
MPC8280 Family -
MC
MC
0
0.1
A.0
0.13 µm
(HiP7)
0K49M
1K49M
2K49M, 3K49M
MPC8272 Family PC
MC
0
A.0
0.13 µm
(HiP7)
0K50M
1K50M

Notes:
1. The IMMR[16-31] indicates the mask number.
2. The Rev_Num located at offset 0x8AF0 in DPRAM indicates the CPM microcode revision number.
3 . Encryption Enabled.
4 . Encryption Disabled.

Masks and versions table last updated on 14OCT2004.

Documentation

Quick reference to our documentation types.

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Design Resources

Hardware

3 hardware offerings

Software

1 software file

Note: For better experience, software downloads are recommended on desktop.

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1 engineering service

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