PowerQUICC® III Processor with DDR2/3

MPC8569E

The MPC8569E PowerQUICC® III family is designed to address the increasing performance requirements for broadband access equipment including 3G/WiMAX/LTE base stations, radio network controllers, gateways and ATM/TDM/IP equipment. The MPC8569E helps facilitate both IP and multi-protocol solutions by combining a high-performance e500 processor core, built on Power Architecture® technology and scaling up to 1.33 GHz, with a flexible communications engine and high-speed system interfaces. The MPC8569E is designed to enable customers to handle many functions in a single-chip solution that otherwise would require multiple devices. This high level of integration provides savings in cost, power and board space.

Product Details

Select a section:

Block Diagram

Freescale PowerQUIICC MPC8569E Communications Processor Block Diagram

NXP<sup>&#174;</sup> PowerQUIICC MPC8569E Communications Processor Block Diagram
Get diagram PDF

Features

  • Embedded e500 core, scaling up to 1.33 GHz
    • 2799 MIPS at 1.33 GHz (estimated Dhrystone 2.1)
    • 36-bit physical addressing
    • Double-precision embedded floating point
    • Memory management unit (MMU)
  • Integrated L1/L2 cache
    • L1 cache—32 KB data and 32 KB instruction
    • L2 cache—512 KB (eight-way set associative)
  • Integrated DDR memory controller with full ECC support
  • Integrated security engine supporting DES, 3DES, MD-5, SHA-1/2, AES, RSA, RNG, Kasumi F8/F9, SNOW, and ARC-4
  • QUICC engine technology
    • Four 32-bit RISC cores
  • Serial RapidIO® and PCI Express® high-speed interconnect interfaces
  • On-chip network switch fabric
  • 166 MHz, 32-bit, 3.3V I/O, enhanced local bus with memory controller
  • Enhanced secured digital host controller (eSDHC) used for SD/MMC card interface
  • Integrated four-channel DMA controller
  • Dual I²C and dual universal asynchronous receiver/transmitter (DUART) support
  • Programmable interrupt controller (PIC)
  • General purpose I/O (GPIO)
  • IEEE® 1149.1 JTAG test access port
  • 1.0V core voltage with 3.3V, 2.5V, 1.8V, 1.5V and 1.0V I/O
  • 783-pin FC-PBGA package, 29 mm x 29 mm
  • This product is included in NXP®.s product longevity program, with assured supply for a minimum of 10 years after launch

    • Documentation

    Quick reference to our documentation types.

    Filters

    1-5 of 43 documents

    Show All

    Design Resources

    Select a section:

    Design Files

    Filters

    1 design file

    Hardware

    Filters

    2 hardware offerings

    Software

    Filters

    2 software files

    Note: For better experience, software downloads are recommended on desktop.

    Engineering Services

    1-5 of 9 engineering services

    Show All

    To find a complete list of our partners that support this product, please see our Partner Marketplace.

    Training

    Filters

    4 trainings

    Support

    What do you need help with?

    Search