Host Processor

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  • This page contains information on a product that is not recommended for new designs.

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Block Diagram

MPC7457 Block Diagram

 MPC7457 Block Diagram

Features

  • Four integer units (3 simple + 1 complex)
  • Double-precision floating-point unit
  • Four AltiVec ® units (simple, complex, floating, and permute)
  • Load/store unit
  • Branch processing unit
  • Footprint compatible with MPC7455 and MPC7445 processors.
  • As with all processors built on Power Architecture technology, the MPC7457 is compatible with the MPC7xx family of processors from NXP®.
  • Processors based on Power Architecture technology enjoy the broadest set of operating systems, compilers, and development tools from third-party tool vendors belonging to NXP Connect partner program.
  • Three issue (plus branch) capability
  • 128-bit wide vector unit—AltiVec technology
  • Integrated 512K on-chip L2 cache (twice the size of previous generation)
  • Full Symmetric Multi-Processing capability (SMP)
  • 36-bit physical address space for direct addressability of 64 Gigabytes of memory
  • Hardware and Software Tablewalk
  • High-bandwidth 133 MHz 64-bit MPX Bus/60x Bus
  • 8 BAT registers
  • Three power-saving user-programmable modes to reduce power drawn by processor
  • Parity checking support on L1, L2 and L3 cache arrays

Documentation

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Design Resources

Design Files

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Engineering Services

3 engineering services

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