MPC7410: Host Processor

Superscalar Microprocessor
MPC7410 microprocessors feature a high-frequency, superscalar Power Architecture processor core, capable of issuing three instructions per clock cycle (two instructions + branch) into eight independent execution units:

• Two integer units and Double-precision floating-point unit
• Vector permute unit
• Vector arithmetic logic unit
• Load/store unit and System unit
• Branch processing unit

MPX Bus Interface
MPC7410 microprocessors support the MPX bus protocol with 64-bit data bus and 32-bit address bus. Support is included for burst, split, pipelined and out-of-order transactions, in addition to data streaming, and data intervention (in SMP systems). The interface provides snooping for data cache coherency. The MPC7410 implements the MERSI cache coherency protocol for multiprocessing support in hardware, allowing access to system memory for additional caching bus leaders, such as DMA devices.

Power Management
MPC7410 microprocessors feature a low-power 1.8-volt design with three power-saving user-programmable modes—nap, doze (with bus snoop) and sleep—which progressively reduce the power drawn by the processor. The MPC7410 also provides a thermal assist unit and instruction cache throttling for software-controllable thermal management.

Cache and MMU Support
The MPC7410 microprocessor has separate 32-Kbyte, physically addressed instruction and data caches. Both caches feature cache locking and are eight-way set-associative. The MPC7410 microprocessor's dedicated L2 cache interface with on-chip L2 tags features a very fast (up to core speed, 1:1) interface to memory, instruction-only or data-only modes, and parity checking on L2 data. The L2 data bus has both 32-bit and 64-bit modes, which can also be configured as private memory. The MPC7410 microprocessor contains separate memory management units (MMUs) for instructions and data, supporting 4 Petabytes (252) of virtual memory and 4 Gigabytes (232) of physical memory. The MPC7410 also has four instruction block address translation (iBAT) and four data block address translation (dBAT) registers.

AltiVec^® Technology
The AltiVec technology expands the capabilities of NXP^® Semiconductors's fourth generation processors by providing leading-edge, general purpose processing performance while concurrently addressing high-bandwidth data processing and algorithmic-intensive computations in a single-chip solution.

AltiVec technology:

• Meets the computational demands of networking infrastructure such as echo cancellation equipment, and basestation processing.
• Enables faster, more secure encryption methods optimized for the SIMD processing model.
• Provides compelling performance for multimedia-oriented desktop computers, desktop publishing, and digital video processing.
• Enables real-time processing of the most demanding data streams (MPEG^®-2 encode, continuous speech recognition, real-time high-resolution 3D memory for additional caching bus leaders, such as DMA devices.)