±2g/±4g/±8g/±16g, Low-Power 12-Bit Digital Accelerometer

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Block Diagram

FXLS8964AF Block Diagram

FXLS8964AF Block Diagram


Compact Package

  • 2 mm x 2 mm x 0.95 mm 10-pin DFN package

Automotive Qualified

  • AEC-Q100, extended temperature range from –40 °C to +105 °C

Robust Design

  • EMC compliant, DFN package with wettable flanks

Low Power

  • ≤ 1 μA IDD up to 6.25 Hz, 20 uA IDD at 400 Hz
  • 650 nA in standby mode
  • 50 nA in hibernate mode

Ultra-Low Power Wake Up

  • Dedicated ultra-low-power motion-detection mode with a single wire interface option

Full-Scale Range

  • ±2 g / ±4 g / ±8 g / ±16 g


  • 12 bit

Output Data Rate

  • 0.78 Hz to 3200 Hz

Communication Interface

  • I2C up to 1 MHz and SPI up to 4 MHz

Configurable Interrupts

  • SDCD block for Freefall, motion or no motion, high-g/low-g, inertial events
  • Vector magnitude
  • Orientation (landscape, portrait, up, down)
  • FIFO/LIFO (144 bytes)
  • Auto-wake sleep for power savings

Bidirectional Self-Test Diagnostic

  • The result is not impacted by device motion or orientation

Product Longevity Program

  • This product is included in the NXP Product Longevity Program ensuring a stable supply of products for your embedded designs. This product is included in the 10-year program.

Part numbers include: FXLS8964AF.


Quick reference to our documentation types.

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Note: For better experience, software downloads are recommended on desktop.

Engineering Services

2 engineering services

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