5-Bit Multiplexed/1-Bit Latched 6-Bit I²C EEPROM DIP Switch

PCA9559PW

The PCA9559 is a 20-pin CMOS device consisting of one 6-bit non-volatile EEPROM registers, 5 hardware pin inputs and a 5-bit multiplexed output with one latched EEPROM bit. It is used for DIP switch-free or jumper-less system configuration and supports Mobile and Desktop VID Configuration, where 2 preset values (1 set of internal non-volatile registers and 1 set of external hardware pins) set processor voltage for operation in either performance or deep sleep modes. The PCA9559 is also useful in server and telecom/networking applications when used to replace DIP switches or jumpers, since the settings can be easily changed via I²C/SMBus without having to power down the equipment to open the cabinet. The non-volatile memory retains the most current setting selected before the power is turned off.

The PCA9559 typically resides between the CPU and Voltage Regulator Module (VRM) when used for CPU VID (Voltage IDentification code) configuration. It is used to bypass the CPU-defined VID values and provide a different set of VID values the VRM, if an increase in the CPU voltage is desired. An increase in CPU voltage combined with an increase in CPU frequency leads to a performance boost of up to 7.5pct. Lower CPU voltage reduces power consumption.

The PCA9559 has 2 address pins allowing up to 4 devices to be placed on the same I²C-bus or SMBus.

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Block Diagram

PCA9559 Block Diagram

PCA9559 Block Diagram
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Features

Key Features

  • 5-bit 2-to-1 multiplexer, 1-bit latch DIP switch
  • 6-bit internal non-volatile register
  • Internal non-volatile register programmable and readable via I2C-bus
  • Override input forces all outputs to logic 0
  • 5 open drain multiplexed outputs
  • 1 open drain non-multiplexed (latched) output
  • 5 V and 2.5 V tolerant inputs
  • Useful for jumperless configuration of PC motherboards
  • 2 address pins, allowing up to 4 devices on the I2C-bus
  • ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per JESD22-A115 and 1000 V CDM per JESD22-C101
  • Latch-up testing is done to JESDEC Standard JESD78 which exceeds 100 mA

Documentation

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Design Files

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  • Models

    PCA9559 IBIS model

    IBSRev 1.0Sep 4, 2014 00:00:0083.3 KBPCA9559_1
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  • Symbols and Footprints

    PCA9559PW-TSSOP20-CAD Symbol and PCB Footprint – BXL File

    ZIPRev 1Sep 22, 2020 17:52:0038.0 KBPCA9559PW-TSSOP20-BXL
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