Quad DSI 2.02 Leader, Differential Drive, Freq Spread

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Block Diagram

Freescale MC33781 Network Transceivers Block Diagram

NXP<sup>&#174;</sup> MC33781 Network Transceivers Block DiagramV

Features

  • Four independent differential DSI (DBUS) channels
  • Dual SPI interface
  • Enhanced bus fault performance
  • Automatic message cyclical redundancy checking (CRC) generation and checking for each channel
  • Enhanced register set with addressable buffer allows queuing of 4 independent follower commands at one time for each channel
  • 8- to 16-Bit messages with 0- to 8-Bit CRC
  • Independent frequency spreading for each channel
  • Pseudo bus switch feature on channel 0

Design Resources

Documentation

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4 documents

Engineering Services

2 engineering services

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