i.MX RT500 Crossover MCU with Arm^® Cortex^®-M33 core

Overview

PRE-PRODUCTION

The i.MX RT500 is a crossover MCU family optimized for low-power HMI application by combining a graphics engine and a streamlined Cadence^® Tensilica^® Fusion F1 DSP core with a next-generation Cortex-M33 core. The i.MX RT500 family of crossover MCUs is designed to unlock the potential of display-based applications with a secure, power-optimized embedded processor.

This page contains information on a preproduction product. Specifications and information here in are subject to change without notice.

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Features

Cortex-M33 core running at a frequency of up to 200 MHz

Arm TrustZone^® for asset protection
Cortex-M33 built-in Memory Protection Unit (MPU) supporting eight regions
Two coprocessors for the Cortex-M33
- PowerQuad hardware accelerator for (fixed and floating point unit) DSP functions
- CASPER crypto co-processor to enable hardware acceleration for various functions required for certain asymmetric cryptographic algorithms

Highly optimized Cadence^® Tensilica^® Fusion F1 DSP processor core running at frequencies of up to 200 MHz

Hardware Floating Point Unit; single-precision IEEE floating point MAC per cycle

On-chip memory

Up to 5 MB of system SRAM accessible by both CPUs and all DMA engines
2 x 32 kB FlexSPI cache

Security features

Secure Isolation: Secure execution environment through Arm^® TrustZone^® technology for ARMv8-M, Symmetric key isolation through hardware engines
Secure Boot supports implemented in boot ROM, providing immutable root of trust
Secure Storage: Physically Unclonable Function (PUF) based key store, On-the-fly-AES decryption (OTFAD) of off-chip flash for code storage
Secure Debug: Certificate-based debug authentication mechanism
Secure Update supports firmware update with authenticity (RSA signed) and confidentiality (AES-CTR encrypted) protection
Hardware Cryptography Accelerators:
- Symmetric cryptography (AES) with 256-bit key strength
- Asymmetric cryptography acceleration
- TRNG with 256-bit entropy
- Hash engine with SHA-256 and SHA-1
Secure Identity: 128-bit Universal Unique Identifier (UUID) and 256-bit Compound Device Identifier (CDI)

Digital peripherals

Two DMA engines, each with 32 channels
Quad/Octal SPI Flash with a dynamic description
Two SD/eMMC memory card interfaces. One supports eMMC 5.0 with HS400/DDR operation
USB high-speed host/device controller with on-chip PHY
Up to 12 configurable universal serial interface modules (FlexComm interfaces) configurable as SPI/I2C/I2S/UART
One high-speed SPI interface supporting 50 MHz operation
Two I3C bus interfaces
A digital microphone interface supporting up to 8 channels

MoreLess

Features

Cortex-M33 core running at a frequency of up to 200 MHz

Arm TrustZone^® for asset protection
Cortex-M33 built-in Memory Protection Unit (MPU) supporting eight regions
Two coprocessors for the Cortex-M33
- PowerQuad hardware accelerator for (fixed and floating point unit) DSP functions
- CASPER crypto co-processor to enable hardware acceleration for various functions required for certain asymmetric cryptographic algorithms

Highly optimized Cadence^® Tensilica^® Fusion F1 DSP processor core running at frequencies of up to 200 MHz

Hardware Floating Point Unit; single-precision IEEE floating point MAC per cycle

On-chip memory

Up to 5 MB of system SRAM accessible by both CPUs and all DMA engines
2 x 32 kB FlexSPI cache

Security features

Secure Isolation: Secure execution environment through Arm^® TrustZone^® technology for ARMv8-M, Symmetric key isolation through hardware engines
Secure Boot supports implemented in boot ROM, providing immutable root of trust
Secure Storage: Physically Unclonable Function (PUF) based key store, On-the-fly-AES decryption (OTFAD) of off-chip flash for code storage
Secure Debug: Certificate-based debug authentication mechanism
Secure Update supports firmware update with authenticity (RSA signed) and confidentiality (AES-CTR encrypted) protection
Hardware Cryptography Accelerators:
- Symmetric cryptography (AES) with 256-bit key strength
- Asymmetric cryptography acceleration
- TRNG with 256-bit entropy
- Hash engine with SHA-256 and SHA-1
Secure Identity: 128-bit Universal Unique Identifier (UUID) and 256-bit Compound Device Identifier (CDI)

Digital peripherals

Two DMA engines, each with 32 channels
Quad/Octal SPI Flash with a dynamic description
Two SD/eMMC memory card interfaces. One supports eMMC 5.0 with HS400/DDR operation
USB high-speed host/device controller with on-chip PHY
Up to 12 configurable universal serial interface modules (FlexComm interfaces) configurable as SPI/I2C/I2S/UART
One high-speed SPI interface supporting 50 MHz operation
Two I3C bus interfaces
A digital microphone interface supporting up to 8 channels

i.MX RT500 Crossover MCU Block Diagram

i.MX RT500 Crossover MCU Block Diagram

i.MX RT500 Crossover MCU with Arm® Cortex®-M33 core

Overview

Features

i.MX RT500 Crossover MCU Block Diagram

i.MX RT500 Crossover MCU Block Diagram

Target Applications

Industrial

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Technologies

i.MX RT500 Crossover MCU with Arm^® Cortex^®-M33 core