Layerscape® 1028A Applications Processor

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Block Diagram

Layerscape LS1028A Block Diagram

Layerscape LS1028A Block Diagram


Core Complex

  • Two 32/64-bit ARM® Cortex®-A72 cores— Up to 1.5 GHz operation
  • Single-threaded cores with 48KB L1 instruction cache and 32KB L1 data cache, Single cluster of two cores sharing 1MB L2 cache

Networking Elements

  • Four SerDes lanes for high-speed peripheral interfaces
  • Ethernet Controller with TSN functionality
  • TSN Capable Ethernet Switch with four external ports
  • Two PCI Express 3.0 controllers (RC or EP)
  • 4 x 2.5 G/1 G switched Eth (TSN enabled)
  • 1 x 2.5 G/1 G Eth (TSN enabled)
  • 1 x 1 G Eth
  • One Serial ATA (SATA 6 Gbit/s) controller

Accelerators and Memory Control

  • 32-bit DDR3L/DDR4 + ECC with speeds up to1.6GT/s
  • One Queue Direct Memory Access Controller (qDMA)
  • One Enhanced Direct Memory Access Controller (eDMA)

Basic Peripherals and Interconnect

  • Two high-speed USB 2.0/3.0 controllers with integrated PHY
  • Two Enhanced Secure Digital Host Controllers (eSDHC) supporting SD 3.0, eMMC 4.4 and eMMC 4.5 and eMMC 5.1
  • Two Controller Area Network (CAN) modules,optionally supporting Flexible Data-rate
  • Three Serial Peripheral Interface (SPI) controllers. One FlexSPI controller
  • Eight I2C controllers
  • One 16550-compliant DUART, Six LPUARTs
  • General Purpose IO (GPIO)
  • Six Synchronous Audio Interface (SAI)

Display and GPU

  • One LCD controller and Display port/eDP interface
  • GPU supporting Geometry rate 100 Mtri/sec, Pixel rate 650 Mpixel/sec, GFLOPS(32-bit high precision) =10.4

Additional Features

  • Thermal Monitor Unit (TMU)
  • FC-PBGA package, 17 mm x 17 mm


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Design Resources


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3 software files

Note: For better experience, software downloads are recommended on desktop.

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