PowerQUICC® III Processor with DDR2/3, eSDHC, PCI, PCI Express, SATA, SerDes, 1 GB Ethernet, USB, Security


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Block Diagram

Freescale PowerQUIICC MPC8535E Communications Processor Block Diagram

NXP<sup>&#174;</sup> PowerQUIICC MPC8535E Communications Processor Block Diagram


  • e500 core, built on Power Architecture® technology, scaling up to 1.25 GHz
  • 32 KB I/D L1 cache
  • 512 KB L2 cache
  • 64-/32-bit DDR2/DDR3 memory controller up to 667 MHz data rate
  • Integrated security engine
    • DES, 3DES, MD-5, SHA-1/2, AES, RSA, RNG, Kasumi F8/F9 and ARC-4 encryption algorithms
  • High-speed interconnects
    • 2 x PCI Express®
    • PCI
  • Advanced power management controller
  • 4 channel DMA controller
  • 2 x I²C
  • eSPI and enhanced local bus
  • GPIO
  • 1 x GbE with SGMII support
  • 2 x USB
  • 1 x SATA multiplexed with SGMII
  • SD/MMC interfaces
  • IEEE® 1588 support
  • 783-pin FC-PBGA package
  • Documentation

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    Design Resources


    2 hardware offerings


    2 software files

    Note: For better experience, software downloads are recommended on desktop.

    Engineering Services

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