The dual-core P5020 and single-core P5010 processors deliver 64-bit processing, based on the e5500 core built on Power Architecture® technology. With frequencies scalable to 2.0 GHz, large caches and high per-cycle efficiency, these products target control plane and computer applications that require high single-threaded performance.
The P5 platform leverages architectural features pioneered in the P4 platform, including the three-level cache hierarchy for low latencies, hardware hypervisor for robust virtualization support, data path acceleration architecture (DPAA) for offloading packet handling tasks from the core and the CoreNet® switch fabric that eliminates internal bottlenecks. This enables architectural compatibility from the P5 platform to the P4 platform as well as to the P3 platform.
| P5020 | P5010 | |
|---|---|---|
| Cores | 2 | 1 |
| Core Frequency | 1.6 to 2.0 GHz | 1.6 to 2.0 GHz |
| L2 Cache | 512 KB | 512 KB |
| L3/Platform Cache | 2 MB | 1 MB |
| DDR3 | 2x 64-bit | 1x 64-bit |
| GbE | 5x 1 GbE 1x 10 GbE | 5x 1 GbE 1x 10 GbE |
| SERDES | 18 Lanes | 18 Lanes |
| Security | Trust | Trust |
Quick reference to our documentation types.
1-5 of 39 documents
2 hardware offerings
1-5 of 6 software files
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1-5 of 11 engineering services
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