QorIQ^® Qonverge BSC9132 Dual-core Processor and Dual-core DSP

Overview

The BSC9132 is a highly integrated device that targets small cell base station, enterprise VoIP, smart grid control, military/defense and industrial applications. The BSC9132 device combines two e500 cores, built on Power Architecture^® technology, and two StarCore^® SC3850 cores with MAPLE-B2P baseband acceleration processing elements to address the need for a high-performance, low-cost, integrated solution that handles a broad range of specialist DSP functions with complimentary high-performance general purpose processing.

For small cell applications, the BSC9132 supports multimode operation with 20 MHz LTE TDD or FDD, and WCDMA 5 MHz.

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Features

Power Architecture subsystem including two e500 processors with 512-Kbyte shared L2 cache
Two StarCore^® SC3850 DSP subsystems, each with a 512-Kbyte private L2 cache
The MAPLE-B2P multi-accelerator platform engine supports functions that enable LTE-FDD/TDD, WiMAX and WCDMA/HSPA+ wireless standards, as well as common DSP function acceleration including FFT, DFT and Turbo Viterbi coding
Two DDR3/3L memory interfaces with 32-bit data width (40 bits including ECC), up to 1333 MHz data rate
Integrated security acceleration (SEC)
Trust architecture secure boot
Two RF interfaces supporting JESD207 (ADI)
Support of MaxPhy interface (Maxim)
Two triple-speed Gigabit-Ethernet controllers featuring network acceleration including IEEE 1588^™ v2 hardware support for two SGMII ports
USB 2.0 host and device controller
Two DUART, Two SPI, and two I2C controllers
Four-lane SerDes PHY that multiplexes the following:
- Two Common Public Radio Interface (CPRI) controller lanes
- USIM interface

MoreLess

Features

Power Architecture subsystem including two e500 processors with 512-Kbyte shared L2 cache
Two StarCore^® SC3850 DSP subsystems, each with a 512-Kbyte private L2 cache
The MAPLE-B2P multi-accelerator platform engine supports functions that enable LTE-FDD/TDD, WiMAX and WCDMA/HSPA+ wireless standards, as well as common DSP function acceleration including FFT, DFT and Turbo Viterbi coding
Two DDR3/3L memory interfaces with 32-bit data width (40 bits including ECC), up to 1333 MHz data rate
Integrated security acceleration (SEC)
Trust architecture secure boot
Two RF interfaces supporting JESD207 (ADI)
Support of MaxPhy interface (Maxim)
Two triple-speed Gigabit-Ethernet controllers featuring network acceleration including IEEE 1588^™ v2 hardware support for two SGMII ports
USB 2.0 host and device controller
Two DUART, Two SPI, and two I2C controllers
Four-lane SerDes PHY that multiplexes the following:
- Two Common Public Radio Interface (CPRI) controller lanes
- USIM interface