QorIQ^® Qonverge BSC9131 Single-core Processor and Single-core DSP

Overview

The QorIQ^® Qonverge BSC9131 processor is a highly integrated device targeting small cell base station, enterprise VoIP, smart grid control, military/defense and industrial applications.

The BSC9131 device combines Power e500 and StarCore^® SC3850 core technologies with MAPLE-B2F specialist DSP acceleration processing, addressing the need for a high-performance, low-cost, integrated solution, that handles a broad range of specialist DSP functions with complimentary high-performance general purpose processing.

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Features

Power Architecture subsystem including one e500 processor and 256-Kbyte shared L2 cache
StarCore^® SC3850 DSP subsystem including 512-Kbyte private L2 cache
The MAPLE-B2F multi-accelerator platform engine supports functions that enable LTE-FDD/TDD, WiMAX, WCDMA/HSPA+ and CDMA2K wireless standards, as well as common DSP function acceleration including FFT, DFT and Turbo Viterbi coding
DDR3 memory interface with 32-bit data width (40 bits including ECC), up to 800-MHz data rate
Integrated Flash controller for NOR, NAND, and FPGA support
Trust architecture secure boot
Integrated security acceleration (SEC)
Two RF interfaces supporting JESD207 (ADI)
Support of MaxPhy interface (Maxim)
Two triple-speed Gigabit-Ethernet controllers featuring network acceleration including IEEE Std 1588v2™ hardware support
USB 2.0 host and device controller
DMA controller with four bidirectional channels that serves both the Power Architecture cores and DSP domains
UART, SPI, eSDHC, USIM, and I2C controllers
GPIO, Sixteen 32-bit timers

MoreLess

Features

Power Architecture subsystem including one e500 processor and 256-Kbyte shared L2 cache
StarCore^® SC3850 DSP subsystem including 512-Kbyte private L2 cache
The MAPLE-B2F multi-accelerator platform engine supports functions that enable LTE-FDD/TDD, WiMAX, WCDMA/HSPA+ and CDMA2K wireless standards, as well as common DSP function acceleration including FFT, DFT and Turbo Viterbi coding
DDR3 memory interface with 32-bit data width (40 bits including ECC), up to 800-MHz data rate
Integrated Flash controller for NOR, NAND, and FPGA support
Trust architecture secure boot
Integrated security acceleration (SEC)
Two RF interfaces supporting JESD207 (ADI)
Support of MaxPhy interface (Maxim)
Two triple-speed Gigabit-Ethernet controllers featuring network acceleration including IEEE Std 1588v2™ hardware support
USB 2.0 host and device controller
DMA controller with four bidirectional channels that serves both the Power Architecture cores and DSP domains
UART, SPI, eSDHC, USIM, and I2C controllers
GPIO, Sixteen 32-bit timers