MCX L14 Ultra-Low-Power MCUs for Always-on Sensing

  • This page contains information on a preproduction product. Specifications and information herein are subject to change without notice. For additional information contact support or your sales representative.

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Block Diagram

MCX L14

MCX-L14-BD

Features

Core Platform

  • Arm Cortex-M33 running up to 48 MHz and Arm Cortex-M0+ running up to 10 MHz

Memory

  • Up to 256 kB on-chip flash program memory with flash accelerator and 4 kB low-power cache
  • Minimum flash programming size: 16 bytes
  • Support Flash Swap with 8 kB granularity
  • Up to 64 KB static random-access memory (SRAM) and an additional 8 kB with ECC capability (supports one-bit correction and two-bit detection)
  • All RAM can be retained down to deep Power-down mode

Peripherals

  • Analog
    • Single‑ended 16‑bit analog-to-digital converter (ADC) with 2.1 MSamples/s rate in 16‑bit mode; supports 12‑bit mode at 2.5 MSamples/s for increased bandwidth
    • Integrated temperature sensor
    • Second 12‑bit ADC (500 kSamples/s) functional down to Deep Power‑down mode
    • One high‑speed comparator with eight input pins and an 8‑bit DAC as an internal reference, functional down to Deep Power‑down mode (can be used as a wake‑up source)
  • Timers
    • Three 32-bit standard general-purpose asynchronous timers/counters, each timer supports up to four capture inputs and four compare outputs; specific timer events can be selected to generate direct memory access (DMA) requests
    • Up to 2x quad timer (QTimer) cascadable with capture and compare capabilities (can be used for quadrature position encoder) that is functional down to Deep Power-down mode
    • Low-power timer (LPTimer)
    • Windowed Watchdog Timer
    • Micro‑Tick Timer running from a 1 MHz clock; wakes device from reduced‑power modes (down to Deep‑sleep with flash off) with extremely low power consumption
    • 42-bit free-running OS timer as continuous timebase for the system, available in any reduced power modes
  • Communication Interfaces
    • 2x Low-power serial peripheral interface (LPSPI) modules, supporting up to 50 MHz operation frequency in master mode
    • Up to 2x Low-power inter-integrated circuit (LPI2C) supporting Standard, Fast, Fast+ and Ultra Fast modes with one additional LPI2C is functional down to Deep Power-down mode
    • Up to 3x LPUART (Low Power UART), provides asynchronous, serial communication capabilities. 1 additional LPUART functional down to Deep Power-down mode

MCUXpresso Developer Experience

Security

  • Glitch attack resistant keyed access (Glikey)
  • Memory block controller (MBC) to Read, Write and Execute permission of each flash block where the configuration can be locked
  • Unique 128‑bit unique device serial number for identification (UUID)
  • Code watchdog for code‑flow integrity detection
  • Three‑level Readout Protection enabling different protection levels across system life‑cycle stages
  • Flash programming through in system programming (ISP) commands over LPUA+B28RT interface with auto baud

Packaging

  • 100 low-profile quad flat package (LQFP), 14x14mm and very thin fine-pitch ball grid array (VFBGA) 90, 6x6 mm

Documentation

Quick reference to our documentation types

1 documents

Compact List

Support

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