1 design file
BSDL for LPC18xx and LPC43xx
The LPC43S20FBD144 is a Arm Cortex-M4 based microcontroller for embedded applications which includes an Arm Cortex-M0 coprocessor, 200 kB of SRAM, security features with AES engine, advanced configurable peripherals such as the State Configurable Timer/PWM (SCTimer/PWM) and the Serial General-Purpose I/O (SGPIO) interface, High-speed USB controller, an external memory controller, and multiple digital and analog peripherals. The LPC43S20FBD144 operates at CPU frequencies of up to 204 MHz.
The Arm Cortex-M4 is a 32-bit core that offers system enhancements such as low power consumption, enhanced debug features, and a high level of support block integration. The Arm Cortex-M4 CPU incorporates a 3-stage pipeline, uses a Harvard architecture with separate local instruction and data buses as well as a third bus for peripherals, and includes an internal prefetch unit that supports speculative branching. The Arm Cortex-M4 supports single-cycle digital signal processing and SIMD instructions. A hardware floating-point unit is integrated in the core.
The Arm Cortex-M0 coprocessor is an energy-efficient and easy-to-use 32-bit core which is code- and tool-compatible with the Cortex-M4 core. The Cortex-M0 coprocessor offers up to 204 MHz performance with a simple instruction set and reduced code size. In LPC43Sx0, the Cortex-M0 coprocessor hardware multiply is implemented as a 32-cycle iterative multiplier.
Quick reference to our documentation types.
1-5 of 18 documents
1 design file
5 hardware offerings
Additional hardware available. View our featured partner solutions.
1-5 of 6 software files
Additional software available. View our featured partner solutions.
Note: For better experience, software downloads are recommended on desktop.
To get further assistance directly from NXP, please see our Engineering Services.
1-5 of 9 engineering services
To find a complete list of our partners that support this product, please see our Partner Marketplace.