Multimedia Applications Processors - Connectivity, Cost Effective, Arm9 Core

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Product Details

Block Diagram

i.MX21S Multimedia Applications Processor Block Diagram

i.MX21S Multimedia Applications Processor Block Diagram

Features

CPU Complex

  • Arm926EJ-S™ core (16 KB I-Cache, 16 KB D-Cache)
  • Arm® Jazelle® technology for Java™ acceleration
  • Smart Speed Switch

Human Interface

  • 16/18-bit color LCD controller up to SVGA
  • Smart panels support (SLCDC)

Connectivity

  • 3 x UARTs, IrDA (SIR, MIR and FIR)
  • USB-OTG (one full-speed host port 2)
  • I²C
  • One wire
  • 8 x 8 keypad
  • Two configurable SPIs

Expansion

  • Dual-slot MMC and SD/SDIO card interface
  • PCMCIA support

Multimedia

  • High-speed CMOS sensor I/F

Special Functions

  • NAND Flash controller
  • 16-channel direct memory access (DMA)
  • 16/32-bit SDRAM controller

Performance

  • CPU complex: starting at 266 MHz
  • System: 133 MHz @ 1.8V

Technology

  • 289 MAPBGA, 14 X 14 mm, 0.65 mm pitch; 17 x 17 mm, 0.8 mm pitch
  • 0.13 µm

Buy/Parametrics










































































































Documentation

Quick reference to our documentation types.

1-10 of 19 documents

Compact List

Application Note (11)
Application Note Software (2)
Data Sheet (1)
Errata (1)
Fact Sheet (1)
Product Brief (1)
Product Change Notice (1)
User Guide (1)

Design Files

Training

2 trainings

Support

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