i.MX507: Multimedia Applications Processors - Low Power Optimization, Integrated Electronic Paper Display (EPD), Arm® Cortex®-A8 Core
Overview
Features
Features
CPU Complex
- Up to 800 MHz Arm® Cortex™-A8
- 32 KB instruction and data caches
- Unified 256 KB L2 cache
- NEON™ SIMD media accelerator
- Vector floating point coprocessor
Multimedia
- 32-bit primary display support up to SXGA+ resolution
- EPD Controller supporting up to 4096 x 4096 resolution
- Pixel Processing Pipeline (ePxP) supporting CSC, Combine, Rotate, Gamma Mapping
Simultaneous EPD and LCD support
- Pixel Processing Pipeline (PxP) supporting CSC, Combine, Rotate, Gamma Mapping
External Memory Interface
- Up to 2GB of LP-DDR2, DDR2 and LP-DDR1(mDDR), 16/32-bit
- SLC/MLC NAND flash, 8/16-bit with 32-bit ECC
Advanced Power Management
- Multiple independent power domains
- State Retention Power Gating (SRPG)
- Dynamic voltage and frequency scaling (DVFS)
Connectivity
- High-Speed USB 2.0 OTG with PHY
- High-Speed USB 2.0 Host with PHY
- 10/100 Ethernet controller
Controllers
- Wide array of serial interfaces, including SDIO, SPI, I2C and UART
- I2S audio interface
Product Longevity
- This product is included in NXP®.s product longevity program, with assured supply for a minimum of 10 years after launch
Development Boards and Designs
Development Boards and Designs
IMX50EVK:i.MX50 Evaluation Kit.
