Multimedia Applications Processors Based on Arm11™ Core

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Block Diagram

i.MX355 Applications Processor Block Diagram

i.MX355 Applications Processor Block Diagram


  • Arm1136JF-S™
  • 532 MHz maximum speed
  • 128 KB Integrated SRAM
  • 16 KB I/D L1 Cache, 128 KB L2 cache
  • MLB
  • ESAI
  • Image Processing Unit (IPU)
  • LCD Controller
  • 10/100 Ethernet
  • MAC 2 x FlexCan modules
  • HS OTG + PHY, HS Host + PHY
  • 3 x UART, 2 x CSPI, 3 I2C, 2 SSI/I2S
  • Optimized for up to 24-bit-per-pixel WVGA
  • CMOS/CCD sensor interface
  • Vector Floating Point Unit
  • External memory interface: mSDRAM/SDRAM, mDDR/DDR2, NOR, SLC/MLC NAND
  • 3.3V general purpose I/O
  • This product is included in NXP®.s product longevity program, with assured supply for a minimum of 15 years after launch


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Design Resources

Design Files

1 design file

  • Models

    IBIS model for rev2_1


1 hardware offering


1 software file

  • Code Snippets


Note: For better experience, software downloads are recommended on desktop.

Engineering Services

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