Multimedia Applications Processors - Connectivity, Cost Effective, Arm9 Core

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Block Diagram

i.MX21S Multimedia Applications Processor Block Diagram

i.MX21S Multimedia Applications Processor Block Diagram


CPU Complex

  • Arm926EJ-S™ core (16 KB I-Cache, 16 KB D-Cache)
  • Arm® Jazelle® technology for Java™ acceleration
  • Smart Speed Switch

Human Interface

  • 16/18-bit color LCD controller up to SVGA
  • Smart panels support (SLCDC)


  • 3 x UARTs, IrDA (SIR, MIR and FIR)
  • USB-OTG (one full-speed host port 2)
  • I2C
  • One wire
  • 8 x 8 keypad
  • Two configurable SPIs


  • Dual-slot MMC and SD/SDIO card interface
  • PCMCIA support


  • High-speed CMOS sensor I/F

Special Functions

  • NAND Flash controller
  • 16-channel direct memory access (DMA)
  • 16/32-bit SDRAM controller


  • CPU complex: starting at 266 MHz
  • System: 133 MHz @ 1.8V


  • 289 MAPBGA, 14 X 14 mm, 0.65 mm pitch; 17 x 17 mm, 0.8 mm pitch
  • 0.13 µm


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