S32R41 High-Performance Processor for High-Resolution Radar

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Block Diagram

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S32R41 Radar MPU

S32R41 Radar MCU Block Diagram

S32R41 Radar MPU App

S32R41 Radar MCU App Block Diagram

S32R41 Software Ecosystem

S32R41 Software Ecosystem


High Performance Safe Compute

  • Arm Cortex-A53 @800 MHz
  • 2x Arm Cortex-M7 @400 MHz with lockstep core configuration (ASIL D capable)

Radar Processing Acceleration

  • SPT 3.5 @600 MHz with integrated DSP

Integration with NXP Radar MMIC’s

  • 2x MIPI CSI2 to connect to NXP TEF82xx

Memory Capacity for Demanding Radar Applications

  • 8 MB SRAM with ECC

Future Proof Security

  • ISO21434 compliant product development
  • In-field updatable Hardware Security Engine (HSE) with comprehensive feature set

Designed with Safety in Mind

Connected and Scalable

  • 2x Ethernet interfaces: 1x RGMII (1000 Mbit/s), 1x RMII (100 Mbit/s)
  • 2x FlexCAN with FD

Full Grade1 Temperature Range Operation

  • -40 °C to 150 °C (Tj) AEC-Q100 Grade-1

Other Features

  • 1x SAR ADC with 8 channels

Product Longevity Program

Software Enablement

Tools, reference and standard software available for download here.

Product Programs


The S32R41 High-Performance processor, part of the EdgeLock Assurance program, is designed to meet industry standards and follows NXP's security-by-design approach.

Safe Assure

When it comes to functional safety, NXP stands for quality and reliability. Our SafeAssure program simplifies system-level safety requirements in accordance with ISO 26262.


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5 documents

Design Resources

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Design Files


2 hardware offerings


3 software files

Note: For better experience, software downloads are recommended on desktop.


2 trainings


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