Low-Power PowerQUICC® II Pro Processor with DDR2, TDM, PCI, Security, USB, QUICC Engine® with UTOPIA

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The MPC8323E PowerQUICC^® II Pro family includes the MPC8323E, MPC8323, MPC8321E and MPC8321. This cost-effective communications processor family meets the requirements of several small office/home office (SOHO), access, IP service and industrial control applications. It provides better CPU performance, additional functionality and faster interfaces than current PowerQUICC II processors while addressing important time to market, price, power consumption and board real estate requirements

Core Complex
The MPC8323E incorporates a unique configuration of the e300c2 (MPC603e-based) core. While this version of e300 core does not have a floating point unit (FPU), it has been designed to include dual integer units as well as a modified multiply instruction. These architectural enhancements enable more efficient operations to be executed in parallel, resulting in significant performance improvement. The core also includes 16 KB of L1 instruction and data caches and on-chip memory management units (MMUs). The MPC8323E also includes a 32-bit PCI controller, four DMA channels, a flexible local bus and a 32-bit DDR-1/DDR-2 SDRAM memory controller.

QUICC Engine^® Technology
A new single-reduced instruction set computing (RISC) version of the QUICC Engine communications engine forms the heart of the networking capability of the MPC8323E. The QUICC Engine block contains several peripheral controllers and a single 32-bit RISC controller. Unique microcode packages provide support for network address port translation (NAT), firewall, IPsec, and advanced quality of service (QoS). Protocol support is provided by the main workhorses of the device—the unified communication controllers (UCCs). Each of the five UCCs can support a variety of communication protocols:

10/100 Mbps Ethernet
Asynchronous transfer mode (ATM) support up to OC-3 speeds
Serial ATM
Multi-physical layer (PHY) ATM
High-level data link control (HDLC)
Time division multiplexing (TDM)
Binary synchronous communications protocol (BISYNC)
UCC can also support USB 2.0 (full/low-speed).

In addition, the QUICC Engine can also support a universal test and operations PHY interface for ATM (UTOPIA) level 2 for up to 31 multi-PHY.

Hardware Security Engine
The security engine (SEC 2.2) on the MPC8323E and MPC8321E allows CPU-intensive cryptographic operations to be off-loaded from the main CPU core. The security-processing accelerator provides hardware acceleration for DES, 3DES, advanced encryption standard (AES), secure hash algorithm (SHA)-1 and MD-5 algorithms.

System Interface Unit
The MPC8323E family also includes a 32-bit double data rate (DDR)-1/DDR/2 memory controller, a 32-bit peripheral component interconnect (PCI) controller, a 16-bit local bus and four direct memory access (DMA) channels

Typical Applications

Residential gateways
SOHO networking
VPN routers
Access points
DSLAM line cards
Industrial control
Test and measurement equipment

Data Sheet

Reference Manual

Product Details

Block Diagram

NXP PowerQUICC MPC8323E Communications Processor Block Diagram

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Features

e300 core built on Power Architecture^® technology with dual integer units enables more efficient operations to be conducted in parallel, resulting in significant performance improvement
The single-RISC QUICC Engine^® communications block offers a future-proof solution for next-generation designs by supporting programmable protocol termination and network interface termination to meet evolving protocol standards
Single-platform architecture supports the convergence of IP packet networks and ATM networks
DDR-1/DDR-2 memory controller—one 32-bit interface operating at up to 266 MHz supporting both DDR-1 and DDR-2
Peripheral interfaces such as 32-bit, 66 MHz PCI, 16-bit, 66 MHz local bus interface and USB 2.0 (full/low speed)
Security engine provides acceleration for control and data plane security protocols
High degree of software compatibility with previous-generation PowerQUICC^® processor-based designs for backward compatibility and easier software migration

Comparison Table

PowerQUICC II Pro Family Comparison

	MPC8321	MPC8321E	MPC8323	MPC8323E
Floating Point Unit	0	0	0	0
H/W Security	No	Sec 2.2	No	Sec 2.2
UTOPIA I/F (8-bit)	No	No	Yes	Yes
I²C	1	1	1	1
QMC Support	up to 64–ch @ 64kbps	up to 64–ch @ 64kbps	up to 64–ch @ 64kbps	up to 64–ch @ 64kbps
Memory Controller (no ECC)	32-bit 266 MHz DDR1/DDR2	32-bit 266 MHz DDR1/DDR2	32-bit 266 MHz DDR1/DDR2	32-bit 266 MHz DDR1/DDR2
QUICC Engine RISC Units	1	1	1	1
QUICC Engine Freq up	up to 200 MHz	up to 200 MHz	up to 200 MHz	up to 200 MHz
Ethernet	up to 3 - 10/100	up to 3 - 10/100	up to 3 - 10/100	up to 3 - 10/100
PCI	32-bit up to 66 MHz	32-bit up to 66 MHz	32-bit up to 66 MHz	32-bit up to 66 MHz
Local bus	16-bit up to 66 MHz	16-bit up to 66 MHz	16-bit up to 66 MHz	16-bit up to 66 MHz
UART	2	2	2	2
USB	USB 2.0 FS/LS	USB 2.0 FS/LS	USB 2.0 FS/LS	USB 2.0 FS/LS
L1 I/D Cache	16KI/16KD	16KI/16KD	16KI/16KD	16KI/16KD
Integer Units	2	2	2	2
TDM I/F	up to 4 – 32ch w/QMC	up to 4 – 32ch w/QMC	up to 4 – 32ch w/QMC	up to 4 – 32ch w/QMC
Package	516-PBGA	516-PBGA	516-PBGA	516-PBGA
Core Frequency	266/333	266/333	266/333	266/333
Core	e300c2	e300c2	e300c2	e300c2

Buy/Parametrics

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Design Resources

Design Files

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Hardware

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2 hardware offerings

Emulators, Probes, and Programmers
Power Architecture^® processor ( COP ) Probe Tips for CodeWarrior^® TAP

CWH-CTP-COP-YE
Emulators, Probes, and Programmers
CodeWarrior^® TAP

CW_TAP

Software

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4 software files

Configuration Tools
UPM Tool for PowerQUICC^® II Pro and PowerQUICC III Processors

ZIPRev 2.3Nov 7, 2007 00:00:002.7 MBLBCUPMIBCG
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BSPs and Device Drivers
Linux BSP for Freescale Freescale MPC8323E MDS PB

ISORev 2Jan 30, 2007 00:00:00480128 KBCWF-MPC8323-MDS-PB

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BSPs and Device Drivers
Linux BSP for Freescale MPC8323E RDB

ISORev 1.1Nov 12, 2008 00:00:00473770 KBCWF-MPC8323E-RDB

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Development IDEs and Build Tools
CodeWarrior^® Development Suites for Networked Applications

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