Low-Cost Microcontrollers (MCUs) Based on Arm® Cortex®-M0+ Cores

LPC86X

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LPC86x is a cost-effective Arm Cortex-M0+ based 32-bit MCU family operating at the frequency of up to 60 MHz and supports up to 64KB of flash memory and up to 8 KB SRAM. This family features a power-optimized core, small footprint in popular packages and level shifting options thanks to its separate power rails. The peripheral complement of the LPC86x includes a CRC engine, I2C-bus interface, I3C-bus interface, up to three USARTs, two SPI interface, one multi-rate timer, self-wake-up timer, two FlexTimer with hardware dead-time insertion and quadrature decoding, one 12-bit ADC, one analog comparator, function-configurable I/O ports through a switch matrix, an input pattern match engine and up to 54 general-purpose I/O pins.

This device is fully supported by NXP’s MCUXpresso Software and Tools, a comprehensive and cohesive set of free software development tools for Kinetis, LPC and i.MX RT microcontrollers. MCUXpresso SDK also includes project files for Keil MDK and IAR EWARM.

Product Details

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Block Diagram

LPC86x MCUs

LPC86x MCUs
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Features

System

  • Arm Cortex-M0+ processor (revision r0p1), running at frequencies of up to 60 MHz with single-cycle multiplier and fast single-cycle I/O port
  • Arm Cortex-M0+ built-in nested vectored interrupt controller (NVIC)
  • System tick timer
  • AHB multilayer matrix
  • Serial wire debug (SWD) with four break points and two watchpoints

Memory

  • 64 kB Flash, small 64 B page size suitable for EEPROM emulation
  • 8 kB RAM (Logic for Bit banding across all of SRAM)

Exceptional Power Efficiency in Low-current Mode Using the FRO as the Clock Source

  • Free running oscillator (FRO)
  • Four power modes
  • Power profile APIs for simple runtime power optimization

FAIM is Used to Configure the Part at Start-up

  • Pin configuration including direction and pull-up or pull-down
  • Clocks and PMU for low-power start-up

Full Range of Timing Features from Basic to Advanced

  • FlexTimer with a total of 10 channels. Hardware dead-time insertion and quadrature decoding for motor control
  • Multi-rate timer (MRT) for repetitive interrupt generation at up to four programmable, fixed rates
  • Self-wake-up timer (WKT) clocked from either Free Running Oscillator (FRO), a low-power, low-frequency internal oscillator or an external clock input
  • Windowed watchdog timer (WWDT)

Accurate 1.9-Msps ADC: 12 ch, 12-bit

  • Ideal for oversampling to improve conversion accuracy
  • Flexible triggers to optimize power use

More Serial Connectivity

  • 1x I3C (support > 10MHz), compatible with I2C
  • 1 x I2C
  • 2 x SPI, 3 x UART
  • 54 GPIO with switch matrix, support input pattern match engine

Documentation

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Design Resources

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Note: For better experience, software downloads are recommended on desktop.