i.MX RT600 Crossover MCU with Arm® Cortex®-M33 and DSP Cores
Overview
Features
Features
Next-generation Cortex-M33 control processor core running at a frequency of up to 300MHz
- Arm TrustZone for asset protection
- Cortex-M33 built-in Memory Protection Unit (MPU) supporting eight regions
- Two coprocessors for the Cortex-M33
- PowerQuad hardware accelerator for (fixed and floating point unit) DSP functions
- CASPER Crypto co-processor is provided to enable hardware acceleration for various functions required for certain asymmetric cryptographic algorithms
Highly Optimized Cadence® Tensilica® HiFi 4 DSP processor core, running at frequencies of up to 600 MHz
- Hardware Floating Point Unit. Up to four single-precision IEEE floating point MACs per cycle
On-chip memory
- Up to 4.5 MB of system SRAM accessible by both CPUs and all DMA engines
- 128 KB of local, Tightly Coupled Memory dedicated to the DSP CPU
- 96 KB of I & D cache for DSP accesses to shared system SRAM
Security features
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Secure Isolation
- Secure execution environment through Arm® TrustZone® technology for ARMv8-M
- Symmetric key isolation through hardware engines
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Secure Boot
- Secure boot support implemented in boot ROM, providing immutable root of trust
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Secure Storage
- Physically Unclonable Function (PUF) based key store
- On-the-fly-AES decryption (OTFAD) of off-chip flash for code storage
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Secure Debug
- Certificate-based debug authentication mechanism
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Secure Update
- Supports firmware update with authenticity (RSA signed) and confidentiality (AES-CTR encrypted) protection
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Hardware Cryptography Accelerators
- Symmetric cryptography (AES) with 256-bit key strength
- Asymmetric cryptography acceleration
- TRNG with 256-bit entropy
- Hash engine with SHA-256 and SHA-1
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Secure Identity
- 128-bit Universal Unique Identifier (UUID) and 256-bit Compound Device Identifier (CDI)
- A member of the EdgeLock Assurance program, providing on-chip security capabilities.
Digital peripherals
- Two DMA engines, each with 32 channels
- Octal/Quad SPI Flash with a dynamic description
- Two SD/eMMC memory card interfaces. One supports eMMC 5.0 with HS400/DDR operation
- USB high-speed host/device controller with on-chip PHY
- Up to eight configurable universal serial interface modules (Flexcomm Interfaces). Configurable as SPI/I2C/I2S/UART
- One high-speed SPI interface supporting 50 MHz operation
- One I3C bus interface
- A digital microphone interface supporting up to 8 channels
i.MX-RT600 Block Diagram
EdgeLock Assurance|The Mark of Security by Design
MCU Minutes | Introducing the i.MX RT600 Crossover MCU
MCU Minutes | Alango Voice Enhancement Package Running on i.MX RT600 Crossover MCUs
MCU Minutes | Audio Playback GUI Demo Using i.MX RT600 Crossover MCU
MCU Tech Minutes: Voice Controlled Audio Player Demo Using NXP’s Voice Intelligent Library (VIT) on i.MX RT600 MCUs
Cellular Connected Edge Device Using NXP's Crossover MCU
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i.MX-RT600 Block Diagram
-
EdgeLock Assurance|The Mark of Security by Design
-
MCU Minutes | Introducing the i.MX RT600 Crossover MCU -
MCU Minutes | Alango Voice Enhancement Package Running on i.MX RT600 Crossover MCUs -
MCU Minutes | Audio Playback GUI Demo Using i.MX RT600 Crossover MCU -
MCU Tech Minutes: Voice Controlled Audio Player Demo Using NXP’s Voice Intelligent Library (VIT) on i.MX RT600 MCUs -
Cellular Connected Edge Device Using NXP's Crossover MCU
i.MX-RT600 Block Diagram
EdgeLock Assurance|The Mark of Security by Design
Development Boards and Designs
Development Boards and Designs
MIMXRT685-EVK:i.MX RT600 Evaluation Kit.
Target Applications
Automotive
- Heating Ventilation, and Air Conditioning (HVAC)
- Motorcycle Engine Control Unit (ECU) and Small Engine Control
Industrial
Mobile
Smart City
Smart Home
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EdgeLock Assurance
The i.MX RT600 crossover MCU, part of the EdgeLock Assurance program, is designed to meet industry standards and follows NXP's security-by-design approach.